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mirror of https://review.coreboot.org/flashrom.git synced 2025-07-01 22:21:16 +02:00

ichspi: Add support for discrete Cannon Lake PCHs

Only minor differences in the Firmware Descriptor, compared to their
predecessors.

We extend our check on the `ICCRIBA` field in the descriptor to dis-
tinguish it from older generation. Alas, the `freq_read` field was
repurposed, so we can't use it as sanity check any more.

Change-Id: I1c2d1e8916cecd756e7ac1f0ba221d7cc361ba02
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Nico Huber
2019-07-04 16:01:51 +02:00
committed by Nico Huber
parent 5ec84b3c09
commit 2a5dfaf140
5 changed files with 87 additions and 32 deletions

View File

@ -133,6 +133,7 @@ static void usage(char *argv[], char *error)
"\t- \"8\" or \"lynx\" for Intel's 8 series chipsets.\n"
"\t- \"9\" or \"wildcat\" for Intel's 9 series chipsets.\n"
"\t- \"100\" or \"sunrise\" for Intel's 100 series chipsets.\n"
"\t- \"300\" or \"cannon\" for Intel's 300 series chipsets.\n"
"If '-d' is specified some regions such as the BIOS image as seen by the CPU or\n"
"the GbE blob that is required to initialize the GbE are also dumped to files.\n",
argv[0], argv[0]);
@ -221,6 +222,9 @@ int main(int argc, char *argv[])
else if ((strcmp(csn, "100") == 0) ||
(strcmp(csn, "sunrise") == 0))
cs = CHIPSET_100_SERIES_SUNRISE_POINT;
else if ((strcmp(csn, "300") == 0) ||
(strcmp(csn, "cannon") == 0))
cs = CHIPSET_300_SERIES_CANNON_POINT;
else if (strcmp(csn, "apollo") == 0)
cs = CHIPSET_APOLLO_LAKE;
}