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chipset_enable: Add support for discrete Cannon Lake PCHs

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The Cannon Lake "300 Series" PCHs [1,2] share the register layout of the
Skylake "100 Series". Mark them as BAD until `ichspi.c` is adapted.

[1] Intel(R) 300 Series and Intel(R) C240 Series
    Chipset Family Platform Controller Hub
    Datasheet - Volume 1 of 2
    Revison 4 (Dec 2018)
    Document Number 337347

[2] Intel(R) 300 Series Chipset Families Platform Controller Hub
    Datasheet - Volume 2 of 2
    Revision 2? (Oct 2018)
    Document Number 337348

Change-Id: If0b54799d5b93169ee660409bad57ae14677340c
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jeremy Soller <jackpot51@gmail.com>
This commit is contained in:
Thomas Heijligen 2019-03-19 17:00:03 +01:00 committed by Nico Huber
parent 045b97ebd9
commit 5ec84b3c09
2 changed files with 19 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
chipset_enable.c
View File

@ -598,6 +598,7 @@ static enum chipbustype enable_flash_ich_report_gcs(
break;
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_APOLLO_LAKE:
reg_name = "BIOS_SPI_BC";
gcs = pci_read_long(dev, 0xdc);
@ -692,6 +693,7 @@ static enum chipbustype enable_flash_ich_report_gcs(
case CHIPSET_9_SERIES_WILDCAT_POINT_LP:
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
boot_straps = boot_straps_pch8_lp;
break;
case CHIPSET_APOLLO_LAKE:
@ -719,6 +721,7 @@ static enum chipbustype enable_flash_ich_report_gcs(
break;
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_APOLLO_LAKE:
bbs = (gcs >> 6) & 0x1;
break;
@ -947,6 +950,11 @@ static int enable_flash_c620(struct pci_dev *const dev, const char *const name)
return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_C620_SERIES_LEWISBURG);
}
static int enable_flash_pch300(struct pci_dev *const dev, const char *const name)
{
return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_300_SERIES_CANNON_POINT);
}
static int enable_flash_apl(struct pci_dev *const dev, const char *const name)
{
return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE);
@ -2027,6 +2035,16 @@ const struct penable chipset_enables[] = {
{0x8086, 0xa2c9, B_S, NT, "Intel", "Z370", enable_flash_pch100},
{0x8086, 0xa2d2, B_S, NT, "Intel", "X299", enable_flash_pch100},
{0x8086, 0x5ae8, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl},
{0x8086, 0xa303, B_S, BAD, "Intel", "H310", enable_flash_pch300},
{0x8086, 0xa304, B_S, BAD, "Intel", "H370", enable_flash_pch300},
{0x8086, 0xa305, B_S, BAD, "Intel", "Z390", enable_flash_pch300},
{0x8086, 0xa306, B_S, BAD, "Intel", "Q370", enable_flash_pch300},
{0x8086, 0xa308, B_S, BAD, "Intel", "B360", enable_flash_pch300},
{0x8086, 0xa309, B_S, BAD, "Intel", "C246", enable_flash_pch300},
{0x8086, 0xa30a, B_S, BAD, "Intel", "C242", enable_flash_pch300},
{0x8086, 0xa30c, B_S, BAD, "Intel", "QM370", enable_flash_pch300},
{0x8086, 0xa30d, B_S, BAD, "Intel", "HM370", enable_flash_pch300},
{0x8086, 0xa30e, B_S, BAD, "Intel", "CM246", enable_flash_pch300},
#endif
{0},
};

1
programmer.h
View File

@ -626,6 +626,7 @@ enum ich_chipset {
CHIPSET_9_SERIES_WILDCAT_POINT_LP,
CHIPSET_100_SERIES_SUNRISE_POINT, /* also 6th/7th gen Core i/o (LP) variants */
CHIPSET_C620_SERIES_LEWISBURG,
CHIPSET_300_SERIES_CANNON_POINT,
CHIPSET_APOLLO_LAKE,
};