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https://review.coreboot.org/flashrom.git
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sbxxx: Add support for new AMD SPI controller
This patch adds support for the "SPI 100" SPI engine in Yangtze FCHs (found in Kabini and Temash). Tested reading/writing on ASRock IMB-A180 and PC Engines' APU board. Corresponding to flashrom svn r1794. Signed-off-by: Wei Hu <wei@aristanetworks.com> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
This commit is contained in:
Wei Hu
Stefan Tauner
parent
d5b2aef69d
commit
31402ee687
2
print.c
2
print.c
@ -577,6 +577,7 @@ const struct board_info boards_known[] = {
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B("ASRock", "G31M-S rev 2.0", OK, "http://www.asrock.com/mb/overview.asp?model=G31M-S", NULL),
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B("ASRock", "H61M-ITX", BAD, "http://www.asrock.com/mb/overview.asp?Model=H61M-ITX", "Probing works (Macronix MX25L3205, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."),
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B("ASRock", "H67M", BAD, "http://www.asrock.com/mb/overview.asp?Model=H67M", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."),
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B("ASRock", "IMB-180-H", OK, "http://www.asrock.com/ipc/overview.asp?Model=IMB-A180-H", NULL),
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B("ASRock", "K7S41", OK, "http://www.asrock.com/mb/overview.asp?Model=K7S41", NULL),
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B("ASRock", "K7S41GX", OK, "http://www.asrock.com/mb/overview.asp?Model=K7S41GX", NULL),
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B("ASRock", "K7VT4A+", BAD, "http://www.asrock.com/mb/overview.asp?Model=K7VT4A%2b", "No chip found, probably due to flash translation. http://www.flashrom.org/pipermail/flashrom/2009-August/000393.html"),
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@ -989,6 +990,7 @@ const struct board_info boards_known[] = {
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B("PC Engines", "Alix.3c3", OK, "http://pcengines.ch/alix3c3.htm", NULL),
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B("PC Engines", "Alix.3d3", OK, "http://pcengines.ch/alix3d3.htm", NULL),
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B("PC Engines", "Alix.6f2", OK, "http://pcengines.ch/alix6f2.htm", NULL),
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B("PC Engines", "APU", OK, "http://pcengines.ch/apu.htm", NULL),
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B("PC Engines", "WRAP.2E", OK, "http://pcengines.ch/wrap2e1.htm", NULL),
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B("PCWARE", "APM80-D3", OK, "http://www.pcwarebr.com.br/produtos_mb_apm80-d3.php", "Probably manufactured by ASUS"),
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B("Pegatron", "IPP7A-CP", OK, NULL, NULL),
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@ -499,6 +499,7 @@ enum spi_controller {
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SPI_CONTROLLER_IT85XX,
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SPI_CONTROLLER_IT87XX,
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SPI_CONTROLLER_SB600,
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SPI_CONTROLLER_YANGTZE,
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SPI_CONTROLLER_VIA,
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SPI_CONTROLLER_WBSIO,
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#endif
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136
sb600spi.c
136
sb600spi.c
@ -4,7 +4,8 @@
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* Copyright (C) 2008 Wang Qingpei <Qingpei.Wang@amd.com>
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* Copyright (C) 2008 Joe Bao <Zheng.Bao@amd.com>
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* Copyright (C) 2008 Advanced Micro Devices, Inc.
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* Copyright (C) 2009, 2010 Carl-Daniel Hailfinger
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* Copyright (C) 2009, 2010, 2013 Carl-Daniel Hailfinger
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* Copyright (C) 2013 Stefan Tauner
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -55,9 +56,12 @@ enum amd_chipset {
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static enum amd_chipset amd_gen = CHIPSET_AMD_UNKNOWN;
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#define FIFO_SIZE_OLD 8
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#define FIFO_SIZE_YANGTZE 71
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static int sb600_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt,
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const unsigned char *writearr, unsigned char *readarr);
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static int spi100_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt,
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const unsigned char *writearr, unsigned char *readarr);
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static struct spi_programmer spi_programmer_sb600 = {
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.type = SPI_CONTROLLER_SB600,
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@ -70,6 +74,17 @@ static struct spi_programmer spi_programmer_sb600 = {
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.write_aai = default_spi_write_aai,
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};
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static struct spi_programmer spi_programmer_yangtze = {
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.type = SPI_CONTROLLER_YANGTZE,
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.max_data_read = FIFO_SIZE_YANGTZE - 3, /* Apparently the big SPI 100 buffer is not a ring buffer. */
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.max_data_write = FIFO_SIZE_YANGTZE - 3,
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.command = spi100_spi_send_command,
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.multicommand = default_spi_send_multicommand,
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.read = default_spi_read,
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.write_256 = default_spi_write_256,
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.write_aai = default_spi_write_aai,
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};
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static void determine_generation(struct pci_dev *dev)
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{
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amd_gen = CHIPSET_AMD_UNKNOWN;
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@ -276,6 +291,45 @@ static int sb600_spi_send_command(struct flashctx *flash, unsigned int writecnt,
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return 0;
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}
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static int spi100_spi_send_command(struct flashctx *flash, unsigned int writecnt,
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unsigned int readcnt,
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const unsigned char *writearr,
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unsigned char *readarr)
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{
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/* First byte is cmd which can not be sent through the buffer. */
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unsigned char cmd = *writearr++;
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writecnt--;
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msg_pspew("%s, cmd=0x%02x, writecnt=%d, readcnt=%d\n", __func__, cmd, writecnt, readcnt);
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mmio_writeb(cmd, sb600_spibar + 0);
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int ret = check_readwritecnt(flash, writecnt, readcnt);
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if (ret != 0)
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return ret;
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/* Use the extended TxByteCount and RxByteCount registers. */
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mmio_writeb(writecnt, sb600_spibar + 0x48);
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mmio_writeb(readcnt, sb600_spibar + 0x4b);
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msg_pspew("Filling buffer: ");
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int count;
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for (count = 0; count < writecnt; count++) {
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msg_pspew("[%02x]", writearr[count]);
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mmio_writeb(writearr[count], sb600_spibar + 0x80 + count);
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}
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msg_pspew("\n");
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execute_command();
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msg_pspew("Reading buffer: ");
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for (count = 0; count < readcnt; count++) {
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readarr[count] = mmio_readb(sb600_spibar + 0x80 + (writecnt + count) % FIFO_SIZE_YANGTZE);
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msg_pspew("[%02x]", readarr[count]);
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}
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msg_pspew("\n");
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return 0;
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}
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struct spispeed {
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const char *const name;
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const uint8_t speed;
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@ -286,6 +340,10 @@ static const struct spispeed spispeeds[] = {
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{ "33 MHz", 0x01 },
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{ "22 MHz", 0x02 },
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{ "16.5 MHz", 0x03 },
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{ "100 MHz", 0x04 },
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{ "Reserved", 0x05 },
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{ "Reserved", 0x06 },
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{ "800 kHz", 0x07 },
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};
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static int set_speed(struct pci_dev *dev, const struct spispeed *spispeed)
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@ -294,7 +352,12 @@ static int set_speed(struct pci_dev *dev, const struct spispeed *spispeed)
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uint8_t speed = spispeed->speed;
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msg_pdbg("Setting SPI clock to %s (0x%x).\n", spispeed->name, speed);
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if (amd_gen != CHIPSET_YANGTZE) {
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if (amd_gen >= CHIPSET_YANGTZE) {
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rmmio_writew((speed << 12) | (speed << 8) | (speed << 4) | speed, sb600_spibar + 0x22);
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uint16_t tmp = mmio_readw(sb600_spibar + 0x22);
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success = (((tmp >> 12) & 0xf) == speed && ((tmp >> 8) & 0xf) == speed &&
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((tmp >> 4) & 0xf) == speed && ((tmp >> 0) & 0xf) == speed);
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} else {
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rmmio_writeb((mmio_readb(sb600_spibar + 0xd) & ~(0x3 << 4)) | (speed << 4), sb600_spibar + 0xd);
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success = (speed == ((mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3));
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}
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@ -306,6 +369,17 @@ static int set_speed(struct pci_dev *dev, const struct spispeed *spispeed)
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return 0;
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}
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static int set_mode(struct pci_dev *dev, uint8_t read_mode)
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{
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uint32_t tmp = mmio_readl(sb600_spibar + 0x00);
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tmp &= ~(0x6 << 28 | 0x1 << 18); /* Clear mode bits */
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tmp |= ((read_mode & 0x6) << 28) | ((read_mode & 0x1) << 18);
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rmmio_writel(tmp, sb600_spibar + 0x00);
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if (tmp != mmio_readl(sb600_spibar + 0x00))
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return 1;
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return 0;
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}
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static int handle_speed(struct pci_dev *dev)
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{
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uint32_t tmp;
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@ -316,7 +390,47 @@ static int handle_speed(struct pci_dev *dev)
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* 18 rsvd <- fastReadEnable ? <- ? SpiReadMode[0]
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* 29:30 rsvd <- <- ? <- ? SpiReadMode[2:1]
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*/
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if (amd_gen != CHIPSET_YANGTZE) {
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if (amd_gen >= CHIPSET_YANGTZE) {
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tmp = mmio_readb(sb600_spibar + 0x20);
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msg_pdbg("UseSpi100 is %sabled\n", (tmp & 0x1) ? "en" : "dis");
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if ((tmp & 0x1) == 0) {
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rmmio_writeb(tmp | 0x1, sb600_spibar + 0x20);
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tmp = mmio_readb(sb600_spibar + 0x20) & 0x1;
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if (tmp == 0) {
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msg_perr("Enabling Spi100 failed.\n");
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return 1;
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}
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msg_pdbg("Enabling Spi100 succeeded.\n");
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}
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static const char *spireadmodes[] = {
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"Normal (up to 33 MHz)", /* 0 */
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"Reserved", /* 1 */
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"Dual IO (1-1-2)", /* 2 */
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"Quad IO (1-1-4)", /* 3 */
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"Dual IO (1-2-2)", /* 4 */
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"Quad IO (1-4-4)", /* 5 */
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"Normal (up to 66 MHz)", /* 6 */
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"Fast Read", /* 7 */
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};
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tmp = mmio_readl(sb600_spibar + 0x00);
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uint8_t read_mode = ((tmp >> 28) & 0x6) | ((tmp >> 18) & 0x1);
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msg_pdbg("SpiReadMode=%s (%i)\n", spireadmodes[read_mode], read_mode);
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if (read_mode != 6) {
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read_mode = 6; /* Default to "Normal (up to 66 MHz)" */
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if (set_mode(dev, read_mode) != 0) {
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msg_perr("Setting read mode to \"%s\" failed.\n", spireadmodes[read_mode]);
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return 1;
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}
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msg_pdbg("Setting read mode to \"%s\" succeeded.\n", spireadmodes[read_mode]);
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}
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tmp = mmio_readw(sb600_spibar + 0x22); /* SPI 100 Speed Config */
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msg_pdbg("NormSpeedNew is %s\n", spispeeds[(tmp >> 12) & 0xf].name);
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msg_pdbg("FastSpeedNew is %s\n", spispeeds[(tmp >> 8) & 0xf].name);
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msg_pdbg("AltSpeedNew is %s\n", spispeeds[(tmp >> 4) & 0xf].name);
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msg_pdbg("TpmSpeedNew is %s\n", spispeeds[(tmp >> 0) & 0xf].name);
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} else {
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if (amd_gen >= CHIPSET_SB89XX && amd_gen <= CHIPSET_HUDSON234) {
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bool fast_read = (mmio_readl(sb600_spibar + 0x00) >> 18) & 0x1;
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msg_pdbg("Fast Reads are %sabled\n", fast_read ? "en" : "dis");
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@ -412,12 +526,6 @@ int sb600_probe_spi(struct pci_dev *dev)
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return ERROR_NONFATAL;
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}
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if (amd_gen == CHIPSET_YANGTZE) {
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msg_perr("SPI on Kabini/Temash and newer chipsets are not yet supported.\n"
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"Please try a newer version of flashrom.\n");
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return ERROR_NONFATAL;
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}
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/* How to read the following table and similar ones in this file:
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* "?" means we have no datasheet for this chipset generation or it doesn't have any relevant info.
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* "<-" means the bit/register meaning is identical to the next non-"?" chipset to the left. "<-" thus
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@ -439,6 +547,8 @@ int sb600_probe_spi(struct pci_dev *dev)
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msg_pdbg("SpiRomEnable=%i", (tmp >> 1) & 0x1);
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if (amd_gen == CHIPSET_SB7XX)
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msg_pdbg(", AltSpiCSEnable=%i, AbortEnable=%i", tmp & 0x1, (tmp >> 2) & 0x1);
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else if (amd_gen == CHIPSET_YANGTZE)
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msg_pdbg(", RouteTpm2Sp=%i", (tmp >> 3) & 0x1);
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tmp = pci_read_byte(dev, 0xba);
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msg_pdbg(", PrefetchEnSPIFromIMC=%i", (tmp & 0x4) >> 2);
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@ -473,6 +583,8 @@ int sb600_probe_spi(struct pci_dev *dev)
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*/
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tmp = mmio_readl(sb600_spibar + 0x00);
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msg_pdbg("(0x%08" PRIx32 ") SpiArbEnable=%i", tmp, (tmp >> 19) & 0x1);
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if (amd_gen == CHIPSET_YANGTZE)
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msg_pdbg(", IllegalAccess=%i", (tmp >> 21) & 0x1);
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msg_pdbg(", SpiAccessMacRomEn=%i, SpiHostAccessRomEn=%i, ArbWaitCount=%i",
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(tmp >> 22) & 0x1, (tmp >> 23) & 0x1, (tmp >> 24) & 0x7);
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@ -485,6 +597,7 @@ int sb600_probe_spi(struct pci_dev *dev)
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msg_pdbg(", DropOneClkOnRd/SpiClkGate=%i", (tmp >> 28) & 0x1);
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case CHIPSET_SB89XX:
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case CHIPSET_HUDSON234:
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case CHIPSET_YANGTZE:
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msg_pdbg(", SpiBusy=%i", (tmp >> 31) & 0x1);
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default: break;
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}
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@ -498,6 +611,7 @@ int sb600_probe_spi(struct pci_dev *dev)
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if (amd_gen >= CHIPSET_SB89XX) {
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tmp = mmio_readb(sb600_spibar + 0x1D);
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msg_pdbg("Using SPI_CS%d\n", tmp & 0x3);
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/* FIXME: Handle SpiProtect* configuration on Yangtze. */
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}
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/* Look for the SMBus device. */
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@ -545,7 +659,11 @@ int sb600_probe_spi(struct pci_dev *dev)
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if (handle_imc(dev) != 0)
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return ERROR_FATAL;
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/* Starting with Yangtze the SPI controller got a different interface with a much bigger buffer. */
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if (amd_gen != CHIPSET_YANGTZE)
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register_spi_programmer(&spi_programmer_sb600);
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else
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register_spi_programmer(&spi_programmer_yangtze);
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return 0;
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}
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