mirror of
https://review.coreboot.org/flashrom.git
synced 2025-04-26 14:42:36 +02:00
sbxxx: Cleanup
- Move programmer definition to the top. - Rewrite array accesses to use indices instead of using pointer arithmetic. - Move length check and opcode extraction to a function. - Move IMC parameter handling into existing IMC handling function. - Split comparing and resetting the FIFO pointer. Corresponding to flashrom svn r1793. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
This commit is contained in:
Stefan Tauner
parent
7141b98649
commit
d5b2aef69d
190
sb600spi.c
190
sb600spi.c
@ -54,6 +54,22 @@ enum amd_chipset {
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};
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static enum amd_chipset amd_gen = CHIPSET_AMD_UNKNOWN;
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#define FIFO_SIZE_OLD 8
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static int sb600_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt,
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const unsigned char *writearr, unsigned char *readarr);
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static struct spi_programmer spi_programmer_sb600 = {
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.type = SPI_CONTROLLER_SB600,
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.max_data_read = FIFO_SIZE_OLD,
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.max_data_write = FIFO_SIZE_OLD - 3,
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.command = sb600_spi_send_command,
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.multicommand = default_spi_send_multicommand,
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.read = default_spi_read,
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.write_256 = default_spi_write_256,
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.write_aai = default_spi_write_aai,
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};
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static void determine_generation(struct pci_dev *dev)
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{
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amd_gen = CHIPSET_AMD_UNKNOWN;
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@ -133,38 +149,45 @@ static void reset_internal_fifo_pointer(void)
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static int compare_internal_fifo_pointer(uint8_t want)
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{
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uint8_t tmp;
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tmp = mmio_readb(sb600_spibar + 0xd) & 0x07;
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want &= 0x7;
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if (want != tmp) {
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msg_perr("FIFO pointer corruption! Pointer is %d, wanted %d\n", tmp, want);
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msg_perr("Something else is accessing the flash chip and "
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"causes random corruption.\nPlease stop all "
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"applications and drivers and IPMI which access the "
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"flash chip.\n");
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uint8_t have = mmio_readb(sb600_spibar + 0xd) & 0x07;
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want %= FIFO_SIZE_OLD;
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if (have != want) {
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msg_perr("AMD SPI FIFO pointer corruption! Pointer is %d, wanted %d\n", have, want);
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msg_perr("Something else is accessing the flash chip and causes random corruption.\n"
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"Please stop all applications and drivers and IPMI which access the flash chip.\n");
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return 1;
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} else {
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msg_pspew("SB600 FIFO pointer is %d, wanted %d\n", tmp, want);
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msg_pspew("AMD SPI FIFO pointer is %d, wanted %d\n", have, want);
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return 0;
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}
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}
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static int reset_compare_internal_fifo_pointer(uint8_t want)
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/* Check the number of bytes to be transmitted and extract opcode. */
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static int check_readwritecnt(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt)
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{
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int ret;
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unsigned int maxwritecnt = flash->pgm->spi.max_data_write + 3;
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if (writecnt > maxwritecnt) {
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msg_pinfo("%s: SPI controller can not send %d bytes, it is limited to %d bytes\n",
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__func__, writecnt, maxwritecnt);
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return SPI_INVALID_LENGTH;
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}
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ret = compare_internal_fifo_pointer(want);
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reset_internal_fifo_pointer();
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return ret;
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unsigned int maxreadcnt = flash->pgm->spi.max_data_read + 3;
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if (readcnt > maxreadcnt) {
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msg_pinfo("%s: SPI controller can not receive %d bytes, it is limited to %d bytes\n",
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__func__, readcnt, maxreadcnt);
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return SPI_INVALID_LENGTH;
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}
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return 0;
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}
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static void execute_command(void)
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{
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msg_pspew("Executing... ");
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mmio_writeb(mmio_readb(sb600_spibar + 2) | 1, sb600_spibar + 2);
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while (mmio_readb(sb600_spibar + 2) & 1)
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;
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msg_pspew("done\n");
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}
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static int sb600_spi_send_command(struct flashctx *flash, unsigned int writecnt,
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@ -172,60 +195,45 @@ static int sb600_spi_send_command(struct flashctx *flash, unsigned int writecnt,
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const unsigned char *writearr,
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unsigned char *readarr)
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{
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int count;
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/* First byte is cmd which can not being sent through FIFO. */
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/* First byte is cmd which can not be sent through the FIFO. */
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unsigned char cmd = *writearr++;
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unsigned int readoffby1;
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unsigned char readwrite;
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writecnt--;
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msg_pspew("%s, cmd=0x%02x, writecnt=%d, readcnt=%d\n", __func__, cmd, writecnt, readcnt);
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mmio_writeb(cmd, sb600_spibar + 0);
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msg_pspew("%s, cmd=%x, writecnt=%x, readcnt=%x\n",
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__func__, cmd, writecnt, readcnt);
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int ret = check_readwritecnt(flash, writecnt, readcnt);
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if (ret != 0)
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return ret;
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if (readcnt > 8) {
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msg_pinfo("%s, SB600 SPI controller can not receive %d bytes, "
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"it is limited to 8 bytes\n", __func__, readcnt);
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return SPI_INVALID_LENGTH;
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}
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if (writecnt > 8) {
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msg_pinfo("%s, SB600 SPI controller can not send %d bytes, "
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"it is limited to 8 bytes\n", __func__, writecnt);
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return SPI_INVALID_LENGTH;
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}
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/* This is a workaround for a bug in SB600 and SB700. If we only send
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/* This is a workaround for a bug in SPI controller. If we only send
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* an opcode and no additional data/address, the SPI controller will
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* read one byte too few from the chip. Basically, the last byte of
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* the chip response is discarded and will not end up in the FIFO.
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* It is unclear if the CS# line is set high too early as well.
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*/
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readoffby1 = (writecnt) ? 0 : 1;
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readwrite = (readcnt + readoffby1) << 4 | (writecnt);
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unsigned int readoffby1 = (writecnt > 0) ? 0 : 1;
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uint8_t readwrite = (readcnt + readoffby1) << 4 | (writecnt);
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mmio_writeb(readwrite, sb600_spibar + 1);
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mmio_writeb(cmd, sb600_spibar + 0);
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/* Before we use the FIFO, reset it first. */
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reset_internal_fifo_pointer();
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/* Send the write byte to FIFO. */
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msg_pspew("Writing: ");
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for (count = 0; count < writecnt; count++, writearr++) {
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msg_pspew("[%02x]", *writearr);
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mmio_writeb(*writearr, sb600_spibar + 0xC);
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msg_pspew("Filling FIFO: ");
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int count;
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for (count = 0; count < writecnt; count++) {
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msg_pspew("[%02x]", writearr[count]);
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mmio_writeb(writearr[count], sb600_spibar + 0xC);
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}
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msg_pspew("\n");
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/*
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* We should send the data by sequence, which means we need to reset
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* the FIFO pointer to the first byte we want to send.
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*/
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if (reset_compare_internal_fifo_pointer(writecnt))
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if (compare_internal_fifo_pointer(writecnt))
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return SPI_PROGRAMMER_ERROR;
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msg_pspew("Executing: \n");
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/*
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* We should send the data in sequence, which means we need to reset
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* the FIFO pointer to the first byte we want to send.
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*/
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reset_internal_fifo_pointer();
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execute_command();
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if (compare_internal_fifo_pointer(writecnt + readcnt))
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return SPI_PROGRAMMER_ERROR;
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/*
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* After the command executed, we should find out the index of the
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@ -238,34 +246,30 @@ static int sb600_spi_send_command(struct flashctx *flash, unsigned int writecnt,
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* the opcode, the FIFO already stores the response from the chip.
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* Usually, the chip will respond with 0x00 or 0xff.
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*/
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if (reset_compare_internal_fifo_pointer(writecnt + readcnt))
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return SPI_PROGRAMMER_ERROR;
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reset_internal_fifo_pointer();
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/* Skip the bytes we sent. */
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msg_pspew("Skipping: ");
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for (count = 0; count < writecnt; count++) {
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cmd = mmio_readb(sb600_spibar + 0xC);
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msg_pspew("[%02x]", cmd);
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msg_pspew("[%02x]", mmio_readb(sb600_spibar + 0xC));
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}
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msg_pspew("\n");
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if (compare_internal_fifo_pointer(writecnt))
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return SPI_PROGRAMMER_ERROR;
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msg_pspew("Reading: ");
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for (count = 0; count < readcnt; count++, readarr++) {
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*readarr = mmio_readb(sb600_spibar + 0xC);
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msg_pspew("[%02x]", *readarr);
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msg_pspew("Reading FIFO: ");
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for (count = 0; count < readcnt; count++) {
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readarr[count] = mmio_readb(sb600_spibar + 0xC);
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msg_pspew("[%02x]", readarr[count]);
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}
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msg_pspew("\n");
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if (reset_compare_internal_fifo_pointer(readcnt + writecnt))
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if (compare_internal_fifo_pointer(writecnt+readcnt))
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return SPI_PROGRAMMER_ERROR;
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if (mmio_readb(sb600_spibar + 1) != readwrite) {
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msg_perr("Unexpected change in SB600 read/write count!\n");
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msg_perr("Something else is accessing the flash chip and "
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"causes random corruption.\nPlease stop all "
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"applications and drivers and IPMI which access the "
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"flash chip.\n");
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msg_perr("Unexpected change in AMD SPI read/write count!\n");
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msg_perr("Something else is accessing the flash chip and causes random corruption.\n"
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"Please stop all applications and drivers and IPMI which access the flash chip.\n");
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return SPI_PROGRAMMER_ERROR;
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}
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@ -328,12 +332,28 @@ static int handle_speed(struct pci_dev *dev)
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return set_speed(dev, &spispeeds[spispeed_idx]);
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}
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static int sb600_handle_imc(struct pci_dev *dev, bool amd_imc_force)
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static int handle_imc(struct pci_dev *dev)
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{
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/* Handle IMC everywhere but sb600 which does not have one. */
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if (amd_gen == CHIPSET_SB6XX)
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return 0;
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bool amd_imc_force = false;
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char *arg = extract_programmer_param("amd_imc_force");
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if (arg && !strcmp(arg, "yes")) {
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amd_imc_force = true;
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msg_pspew("amd_imc_force enabled.\n");
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} else if (arg && !strlen(arg)) {
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msg_perr("Missing argument for amd_imc_force.\n");
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free(arg);
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return 1;
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} else if (arg) {
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msg_perr("Unknown argument for amd_imc_force: \"%s\" (not \"yes\").\n", arg);
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free(arg);
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return 1;
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}
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free(arg);
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/* TODO: we should not only look at IntegratedImcPresent (LPC Dev 20, Func 3, 40h) but also at
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* IMCEnable(Strap) and Override EcEnable(Strap) (sb8xx, sb9xx?, a50: Misc_Reg: 80h-87h;
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* sb7xx, sp5100: PM_Reg: B0h-B1h) etc. */
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@ -361,38 +381,11 @@ static int sb600_handle_imc(struct pci_dev *dev, bool amd_imc_force)
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return amd_imc_shutdown(dev);
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}
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static const struct spi_programmer spi_programmer_sb600 = {
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.type = SPI_CONTROLLER_SB600,
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.max_data_read = 8,
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.max_data_write = 5,
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.command = sb600_spi_send_command,
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.multicommand = default_spi_send_multicommand,
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.read = default_spi_read,
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.write_256 = default_spi_write_256,
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.write_aai = default_spi_write_aai,
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};
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int sb600_probe_spi(struct pci_dev *dev)
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{
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struct pci_dev *smbus_dev;
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uint32_t tmp;
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uint8_t reg;
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bool amd_imc_force = false;
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char *arg = extract_programmer_param("amd_imc_force");
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if (arg && !strcmp(arg, "yes")) {
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amd_imc_force = true;
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msg_pspew("amd_imc_force enabled.\n");
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} else if (arg && !strlen(arg)) {
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msg_perr("Missing argument for amd_imc_force.\n");
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free(arg);
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return ERROR_FATAL;
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} else if (arg) {
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msg_perr("Unknown argument for amd_imc_force: \"%s\" (not \"yes\").\n", arg);
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free(arg);
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return ERROR_FATAL;
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}
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free(arg);
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/* Read SPI_BaseAddr */
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tmp = pci_read_long(dev, 0xa0);
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@ -549,12 +542,9 @@ int sb600_probe_spi(struct pci_dev *dev)
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if (handle_speed(dev) != 0)
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return ERROR_FATAL;
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if (sb600_handle_imc(dev, amd_imc_force) != 0)
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if (handle_imc(dev) != 0)
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return ERROR_FATAL;
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/* Bring the FIFO to a clean state. */
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reset_internal_fifo_pointer();
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register_spi_programmer(&spi_programmer_sb600);
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return 0;
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}
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