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sb600spi: Fix Promontory flash read of chips larger than 16MiB

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If the flash chip is larger than 16MiB, the memory mapped read from
top of 4G address will not work properly, resulting in accesses
to addresses below 0xff000000. In such cases flashrom fails with
"Bus error".

Fallback to default_spi_read for flashes larger than 16 MiB. Using
memory mapped access with ROM3 register could be implemented, however
it introduces the complexity of ROM page remapping. I.e. the PSP may
remap 16MiB pages of 32MiB or larger flashes by XORing the host
memory mapped address bits [31:24]. It results in non-linear memory
mapped flash space.

Fixes the issue: https://ticket.coreboot.org/issues/370

TEST=Read complete flash content on Gigabyte MZ33-AR1 running coreboot.

Change-Id: I218a4c2dbf7cd7e8fa25b3ecb5aeac03f54f9dc6
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/89446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
This commit is contained in:
Michał Żygowski
2025-10-07 13:39:19 +02:00
committed by Anastasia Klimchuk
parent 3471cba18a
commit 3461f65b23
2 changed files with 11 additions and 7 deletions
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11
doc/release_notes/devel.rst
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@@ -7,13 +7,12 @@ the next release of flashrom and which are currently only available by source
code checkout (see :doc:`../dev_guide/building_from_source`). These changes code checkout (see :doc:`../dev_guide/building_from_source`). These changes
may be further revised before the next release. may be further revised before the next release.
Known issues Bugs fixed
============ ==========
AMD-based PCs with FCH are unable to read flash contents for internal (BIOS AMD-based PCs with FCH were unable to read flash contents for internal (BIOS
flash) chips larger than 16 MB, and attempting to do so may crash the system. flash) chips larger than 16 MB, and attempting to do so could crash the
Systems with AMD "Promontory" IO extenders (mostly "Zen" desktop platforms) are system.
not currently supported.
https://ticket.coreboot.org/issues/370 https://ticket.coreboot.org/issues/370

7
sb600spi.c
View File

@@ -575,6 +575,11 @@ static int promontory_read_memmapped(struct flashctx *flash, uint8_t *buf,
unsigned int start, unsigned int len) unsigned int start, unsigned int len)
{ {
struct sb600spi_data * data = (struct sb600spi_data *)flash->mst->spi.data; struct sb600spi_data * data = (struct sb600spi_data *)flash->mst->spi.data;
/* If the flash size is bigger than 16MiB, we can't read it from the top of 4G */
if (flash->chip->total_size > (16 * 1024))
return default_spi_read(flash, buf, start, len);
if (!data->flash) { if (!data->flash) {
map_flash(flash); map_flash(flash);
data->flash = flash; /* keep a copy of flashctx for unmap() on tear-down. */ data->flash = flash; /* keep a copy of flashctx for unmap() on tear-down. */
@@ -617,7 +622,7 @@ static const struct spi_master spi_master_yangtze = {
}; };
static const struct spi_master spi_master_promontory = { static const struct spi_master spi_master_promontory = {
.max_data_read = MAX_DATA_READ_UNLIMITED, .max_data_read = FIFO_SIZE_YANGTZE - 3,
.max_data_write = FIFO_SIZE_YANGTZE - 3, .max_data_write = FIFO_SIZE_YANGTZE - 3,
.command = spi100_spi_send_command, .command = spi100_spi_send_command,
.map_flash_region = physmap, .map_flash_region = physmap,