mirror of
https://review.coreboot.org/flashrom.git
synced 2025-04-26 22:52:34 +02:00
Check vendor_id for PCI based external programmers
Restructure PCI device detection code. Rename pcidev_validate to pcidev_readbar. Note: Slight changes in behaviour are possible, especially on dual/quad chip NICs which appear as more than one PCI device. Found devices are no longer printed at _pinfo level, but rather at _pdbg level. Corresponding to flashrom svn r1548. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
This commit is contained in:
Carl-Daniel Hailfinger
parent
6e48a026f7
commit
3834c2d7e5
@ -87,7 +87,7 @@ int nicintel_init(void)
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goto error_out_unmap;
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/* FIXME: Using pcidev_dev _will_ cause pretty explosions in the future. */
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addr = pcidev_validate(pcidev_dev, PCI_BASE_ADDRESS_0, nics_intel);
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addr = pcidev_readbar(pcidev_dev, PCI_BASE_ADDRESS_0);
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/* FIXME: This is not an aligned mapping. Use 4k? */
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nicintel_control_bar = physmap("Intel NIC control/status reg",
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addr, NICINTEL_CONTROL_MEMMAP_SIZE);
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259
pcidev.c
259
pcidev.c
@ -35,157 +35,122 @@ enum pci_bartype {
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TYPE_UNKNOWN
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};
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uintptr_t pcidev_validate(struct pci_dev *dev, int bar,
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const struct pcidev_status *devs)
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uintptr_t pcidev_readbar(struct pci_dev *dev, int bar)
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{
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int i;
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uint64_t addr;
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uint32_t upperaddr;
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uint8_t headertype;
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uint16_t supported_cycles;
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enum pci_bartype bartype = TYPE_UNKNOWN;
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for (i = 0; devs[i].device_name != NULL; i++) {
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if (dev->device_id != devs[i].device_id)
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continue;
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msg_pinfo("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x).\n",
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devs[i].vendor_name, devs[i].device_name,
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dev->vendor_id, dev->device_id, dev->bus, dev->dev,
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dev->func);
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headertype = pci_read_byte(dev, PCI_HEADER_TYPE) & 0x7f;
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msg_pspew("PCI header type 0x%02x\n", headertype);
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headertype = pci_read_byte(dev, PCI_HEADER_TYPE) & 0x7f;
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msg_pspew("PCI header type 0x%02x\n", headertype);
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/* Don't use dev->base_addr[x] (as value for 'bar'), won't work on older libpci. */
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addr = pci_read_long(dev, bar);
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/*
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* Don't use dev->base_addr[x] (as value for 'bar'), won't
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* work on older libpci.
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*/
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addr = pci_read_long(dev, bar);
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/* Sanity checks. */
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switch (headertype) {
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case PCI_HEADER_TYPE_NORMAL:
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switch (bar) {
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case PCI_BASE_ADDRESS_0:
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case PCI_BASE_ADDRESS_1:
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case PCI_BASE_ADDRESS_2:
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case PCI_BASE_ADDRESS_3:
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case PCI_BASE_ADDRESS_4:
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case PCI_BASE_ADDRESS_5:
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if ((addr & PCI_BASE_ADDRESS_SPACE) ==
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PCI_BASE_ADDRESS_SPACE_IO)
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bartype = TYPE_IOBAR;
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else
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bartype = TYPE_MEMBAR;
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break;
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case PCI_ROM_ADDRESS:
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bartype = TYPE_ROMBAR;
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break;
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}
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/* Sanity checks. */
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switch (headertype) {
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case PCI_HEADER_TYPE_NORMAL:
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switch (bar) {
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case PCI_BASE_ADDRESS_0:
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case PCI_BASE_ADDRESS_1:
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case PCI_BASE_ADDRESS_2:
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case PCI_BASE_ADDRESS_3:
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case PCI_BASE_ADDRESS_4:
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case PCI_BASE_ADDRESS_5:
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if ((addr & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO)
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bartype = TYPE_IOBAR;
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else
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bartype = TYPE_MEMBAR;
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break;
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case PCI_HEADER_TYPE_BRIDGE:
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switch (bar) {
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case PCI_BASE_ADDRESS_0:
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case PCI_BASE_ADDRESS_1:
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if ((addr & PCI_BASE_ADDRESS_SPACE) ==
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PCI_BASE_ADDRESS_SPACE_IO)
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bartype = TYPE_IOBAR;
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else
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bartype = TYPE_MEMBAR;
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break;
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case PCI_ROM_ADDRESS1:
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bartype = TYPE_ROMBAR;
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break;
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}
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break;
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case PCI_HEADER_TYPE_CARDBUS:
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break;
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default:
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msg_perr("Unknown PCI header type 0x%02x, BAR type "
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"cannot be determined reliably.\n", headertype);
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case PCI_ROM_ADDRESS:
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bartype = TYPE_ROMBAR;
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break;
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}
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supported_cycles = pci_read_word(dev, PCI_COMMAND);
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msg_pdbg("Requested BAR is ");
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switch (bartype) {
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case TYPE_MEMBAR:
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msg_pdbg("MEM");
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if (!(supported_cycles & PCI_COMMAND_MEMORY)) {
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msg_perr("MEM BAR access requested, but device "
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"has MEM space accesses disabled.\n");
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/* TODO: Abort here? */
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}
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msg_pdbg(", %sbit, %sprefetchable\n",
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((addr & 0x6) == 0x0) ? "32" :
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(((addr & 0x6) == 0x4) ? "64" : "reserved"),
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(addr & 0x8) ? "" : "not ");
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if ((addr & 0x6) == 0x4) {
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/* The spec says that a 64-bit register consumes
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* two subsequent dword locations.
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*/
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upperaddr = pci_read_long(dev, bar + 4);
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if (upperaddr != 0x00000000) {
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/* Fun! A real 64-bit resource. */
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if (sizeof(uintptr_t) != sizeof(uint64_t)) {
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msg_perr("BAR unreachable!");
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/* TODO: Really abort here? If
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* multiple PCI devices match,
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* we might never tell the user
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* about the other devices.
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*/
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return 0;
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}
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addr |= (uint64_t)upperaddr << 32;
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}
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}
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addr &= PCI_BASE_ADDRESS_MEM_MASK;
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break;
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case PCI_HEADER_TYPE_BRIDGE:
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switch (bar) {
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case PCI_BASE_ADDRESS_0:
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case PCI_BASE_ADDRESS_1:
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if ((addr & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO)
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bartype = TYPE_IOBAR;
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else
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bartype = TYPE_MEMBAR;
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break;
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case TYPE_IOBAR:
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msg_pdbg("I/O\n");
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#if __FLASHROM_HAVE_OUTB__
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if (!(supported_cycles & PCI_COMMAND_IO)) {
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msg_perr("I/O BAR access requested, but device "
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"has I/O space accesses disabled.\n");
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/* TODO: Abort here? */
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}
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#else
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msg_perr("I/O BAR access requested, but flashrom does "
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"not support I/O BAR access on this platform "
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"(yet).\n");
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#endif
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addr &= PCI_BASE_ADDRESS_IO_MASK;
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case PCI_ROM_ADDRESS1:
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bartype = TYPE_ROMBAR;
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break;
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case TYPE_ROMBAR:
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msg_pdbg("ROM\n");
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/* Not sure if this check is needed. */
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if (!(supported_cycles & PCI_COMMAND_MEMORY)) {
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msg_perr("MEM BAR access requested, but device "
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"has MEM space accesses disabled.\n");
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/* TODO: Abort here? */
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}
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addr &= PCI_ROM_ADDRESS_MASK;
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break;
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case TYPE_UNKNOWN:
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msg_perr("BAR type unknown, please report a bug at "
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"flashrom@flashrom.org\n");
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}
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if (devs[i].status == NT) {
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msg_pinfo("===\nThis PCI device is UNTESTED. Please "
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"report the 'flashrom -p xxxx' output \n"
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"to flashrom@flashrom.org if it works "
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"for you. Please add the name of your\n"
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"PCI device to the subject. Thank you for "
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"your help!\n===\n");
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}
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return (uintptr_t)addr;
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break;
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case PCI_HEADER_TYPE_CARDBUS:
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break;
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default:
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msg_perr("Unknown PCI header type 0x%02x, BAR type cannot be determined reliably.\n",
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headertype);
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break;
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}
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return 0;
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supported_cycles = pci_read_word(dev, PCI_COMMAND);
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msg_pdbg("Requested BAR is ");
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switch (bartype) {
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case TYPE_MEMBAR:
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msg_pdbg("MEM");
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if (!(supported_cycles & PCI_COMMAND_MEMORY)) {
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msg_perr("MEM BAR access requested, but device has MEM space accesses disabled.\n");
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/* TODO: Abort here? */
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}
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msg_pdbg(", %sbit, %sprefetchable\n",
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((addr & 0x6) == 0x0) ? "32" : (((addr & 0x6) == 0x4) ? "64" : "reserved"),
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(addr & 0x8) ? "" : "not ");
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if ((addr & 0x6) == 0x4) {
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/* The spec says that a 64-bit register consumes
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* two subsequent dword locations.
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*/
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upperaddr = pci_read_long(dev, bar + 4);
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if (upperaddr != 0x00000000) {
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/* Fun! A real 64-bit resource. */
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if (sizeof(uintptr_t) != sizeof(uint64_t)) {
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msg_perr("BAR unreachable!");
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/* TODO: Really abort here? If multiple PCI devices match,
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* we might never tell the user about the other devices.
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*/
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return 0;
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}
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addr |= (uint64_t)upperaddr << 32;
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}
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}
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addr &= PCI_BASE_ADDRESS_MEM_MASK;
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break;
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case TYPE_IOBAR:
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msg_pdbg("I/O\n");
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#if __FLASHROM_HAVE_OUTB__
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if (!(supported_cycles & PCI_COMMAND_IO)) {
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msg_perr("I/O BAR access requested, but device has I/O space accesses disabled.\n");
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/* TODO: Abort here? */
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}
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#else
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msg_perr("I/O BAR access requested, but flashrom does not support I/O BAR access on this "
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"platform (yet).\n");
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#endif
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addr &= PCI_BASE_ADDRESS_IO_MASK;
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break;
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case TYPE_ROMBAR:
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msg_pdbg("ROM\n");
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/* Not sure if this check is needed. */
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if (!(supported_cycles & PCI_COMMAND_MEMORY)) {
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msg_perr("MEM BAR access requested, but device has MEM space accesses disabled.\n");
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/* TODO: Abort here? */
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}
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addr &= PCI_ROM_ADDRESS_MASK;
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break;
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case TYPE_UNKNOWN:
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msg_perr("BAR type unknown, please report a bug at flashrom@flashrom.org\n");
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}
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return (uintptr_t)addr;
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}
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uintptr_t pcidev_init(int bar, const struct pcidev_status *devs)
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@ -195,6 +160,7 @@ uintptr_t pcidev_init(int bar, const struct pcidev_status *devs)
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char *pcidev_bdf;
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char *msg = NULL;
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int found = 0;
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int i;
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uintptr_t addr = 0, curaddr = 0;
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pacc = pci_alloc(); /* Get the pci_access structure */
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@ -214,10 +180,29 @@ uintptr_t pcidev_init(int bar, const struct pcidev_status *devs)
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for (dev = pacc->devices; dev; dev = dev->next) {
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if (pci_filter_match(&filter, dev)) {
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/* Check against list of supported devices. */
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for (i = 0; devs[i].device_name != NULL; i++)
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if ((dev->vendor_id == devs[i].vendor_id) &&
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(dev->device_id == devs[i].device_id))
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break;
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/* Not supported, try the next one. */
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if (devs[i].device_name == NULL)
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continue;
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msg_pdbg("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x).\n", devs[i].vendor_name,
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devs[i].device_name, dev->vendor_id, dev->device_id, dev->bus, dev->dev,
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dev->func);
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if (devs[i].status == NT)
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msg_pinfo("===\nThis PCI device is UNTESTED. Please report the 'flashrom -p "
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"xxxx' output \n"
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"to flashrom@flashrom.org if it works for you. Please add the name "
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"of your\n"
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"PCI device to the subject. Thank you for your help!\n===\n");
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/* FIXME: We should count all matching devices, not
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* just those with a valid BAR.
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*/
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if ((addr = pcidev_validate(dev, bar, devs)) != 0) {
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if ((addr = pcidev_readbar(dev, bar)) != 0) {
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curaddr = addr;
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pcidev_dev = dev;
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found++;
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@ -230,10 +215,8 @@ uintptr_t pcidev_init(int bar, const struct pcidev_status *devs)
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msg_perr("Error: No supported PCI device found.\n");
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exit(1);
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} else if (found > 1) {
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msg_perr("Error: Multiple supported PCI devices found. "
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"Use 'flashrom -p xxxx:pci=bb:dd.f' \n"
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"to explicitly select the card with the given BDF "
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"(PCI bus, device, function).\n");
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msg_perr("Error: Multiple supported PCI devices found. Use 'flashrom -p xxxx:pci=bb:dd.f' \n"
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"to explicitly select the card with the given BDF (PCI bus, device, function).\n");
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exit(1);
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}
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@ -227,7 +227,7 @@ struct pcidev_status {
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const char *vendor_name;
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const char *device_name;
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};
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uintptr_t pcidev_validate(struct pci_dev *dev, int bar, const struct pcidev_status *devs);
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uintptr_t pcidev_readbar(struct pci_dev *dev, int bar);
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uintptr_t pcidev_init(int bar, const struct pcidev_status *devs);
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/* rpci_write_* are reversible writes. The original PCI config space register
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* contents will be restored on shutdown.
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