mirror of
https://review.coreboot.org/flashrom.git
synced 2025-04-27 07:02:34 +02:00
Fix compilation of nic3com on 64bit
Corresponding to flashrom svn r512. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
This commit is contained in:
parent
a086932cf9
commit
3b7e75a23e
1
flash.h
1
flash.h
@ -585,6 +585,7 @@ void *physmap(const char *descr, unsigned long phys_addr, size_t len);
|
||||
void physunmap(void *virt_addr, size_t len);
|
||||
|
||||
/* internal.c */
|
||||
void get_io_perms(void);
|
||||
int internal_init(void);
|
||||
int internal_shutdown(void);
|
||||
void internal_chip_writeb(uint8_t val, volatile void *addr);
|
||||
|
@ -102,7 +102,7 @@ int internal_init(void)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
get_io_perms(void);
|
||||
get_io_perms();
|
||||
|
||||
/* Initialize PCI access for flash enables */
|
||||
pacc = pci_alloc(); /* Get the pci_access structure */
|
||||
|
@ -158,7 +158,7 @@ void nic3com_unmap(void *virt_addr, size_t len)
|
||||
|
||||
void nic3com_chip_writeb(uint8_t val, volatile void *addr)
|
||||
{
|
||||
OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
|
||||
OUTL((uint32_t)(intptr_t)addr, io_base_addr + BIOS_ROM_ADDR);
|
||||
OUTB(val, io_base_addr + BIOS_ROM_DATA);
|
||||
}
|
||||
|
||||
@ -174,7 +174,7 @@ uint8_t nic3com_chip_readb(const volatile void *addr)
|
||||
{
|
||||
uint8_t val;
|
||||
|
||||
OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
|
||||
OUTL((uint32_t)(intptr_t)addr, io_base_addr + BIOS_ROM_ADDR);
|
||||
val = INB(io_base_addr + BIOS_ROM_DATA);
|
||||
|
||||
return val;
|
||||
|
Loading…
x
Reference in New Issue
Block a user