mirror of
https://review.coreboot.org/flashrom.git
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Update the ITE IT8500 EC support to match the current state of the flashrom-chromium tree
This code has been deployed and tested to work on the Cr-48. There are a few caveats, though: - The boot BIOS straps register must be modified to select LPC. This can be done with the "select_bbs.sh" script (Install iotools at http://code.google.com/p/iotools/ before using select_bbs). - It is very important to disable power management daemons before running flashrom on this EC. I commented out the brute force method we use in the Chromium OS branch that disables powerd, since IIRC Carl-Daniel has a better approach in the works. - Due to dependencies which may be introduced by the OEM/ODM EC firmware, the code is not guaranteed to work for anything other than the Cr-48. Corresponding to flashrom svn r1263. Signed-off-by: David Hendricks <dhendrix@google.com> Carl-Daniel comments: Code is not hooked up yet because probing needs to be sorted out. Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
This commit is contained in:
David Hendricks
Carl-Daniel Hailfinger
parent
44ebb04f9f
commit
4e74839646
2
Makefile
2
Makefile
@ -184,7 +184,7 @@ ifeq ($(CONFIG_INTERNAL), yes)
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FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1'
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PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o
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# FIXME: The PROGRAMMER_OBJS below should only be included on x86.
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PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o
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PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o
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NEED_PCI := yes
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endif
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171
it85spi.c
171
it85spi.c
@ -27,18 +27,23 @@
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#if defined(__i386__) || defined(__x86_64__)
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#include <string.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include "flash.h"
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#include "chipdrivers.h"
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#include "spi.h"
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#include "programmer.h"
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#define MAX_TIMEOUT 100000
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#define MAX_TRY 5
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/* Constans for I/O ports */
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#define ITE_SUPERIO_PORT1 0x2e
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#define ITE_SUPERIO_PORT2 0x4e
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/* Legacy I/O */
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#define LEGACY_KBC_PORT 0x64
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#define LEGACY_KBC_PORT_DATA 0x60
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#define LEGACY_KBC_PORT_CMD 0x64
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/* Constants for Logical Device registers */
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#define LDNSEL 0x07
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@ -50,6 +55,13 @@
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#define SHM_IO_BAD0 0x60 /* big-endian, this is high bits */
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#define SHM_IO_BAD1 0x61
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/* 8042 keyboard controller uses an input buffer and an output buffer to
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* communicate with host CPU. Both buffers are 1-byte depth. That means the
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* IBF is set to 1 when host CPU sends a command to input buffer (standing on
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* the EC side). IBF is cleared to 0 once the command is read by EC. */
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#define KB_IBF (1 << 1) /* Input Buffer Full */
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#define KB_OBF (1 << 0) /* Output Buffer Full */
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/* IT8502 supports two access modes:
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* LPC_MEMORY: through the memory window in 0xFFFFFxxx (follow mode)
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* LPC_IO: through I/O port (so called indirect memory)
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@ -95,11 +107,11 @@ struct superio probe_superio_ite85xx(void)
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ret.model = probe_id_ite85(ret.port);
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switch (ret.model >> 8) {
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case 0x85:
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msg_pinfo("Found EC: ITE85xx (Vendor:0x%02x,ID:0x%02x,"
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"Rev:0x%02x) on sio_port:0x%x.\n",
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ret.model >> 8, ret.model & 0xff,
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sio_read(ret.port, CHIP_CHIP_VER_REG),
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ret.port);
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msg_pdbg("Found EC: ITE85xx (Vendor:0x%02x,ID:0x%02x,"
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"Rev:0x%02x) on sio_port:0x%x.\n",
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ret.model >> 8, ret.model & 0xff,
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sio_read(ret.port, CHIP_CHIP_VER_REG),
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ret.port);
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return ret;
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}
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}
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@ -111,20 +123,147 @@ struct superio probe_superio_ite85xx(void)
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return ret;
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}
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/* IT8502 employs a scratch rom when flash is updating. Call the following two
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* functions before/after flash erase/program. */
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/* This function will poll the keyboard status register until either
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* an expected value shows up, or
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* timeout reaches.
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*
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* Returns: 0 -- the expected value has shown.
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* 1 -- timeout reached.
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*/
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static int wait_for(
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const unsigned int mask,
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const unsigned int expected_value,
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const int timeout, /* in usec */
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const char* error_message,
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const char* function_name,
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const int lineno
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) {
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int time_passed;
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for (time_passed = 0;; ++time_passed) {
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if ((INB(LEGACY_KBC_PORT_CMD) & mask) == expected_value)
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return 0;
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if (time_passed >= timeout)
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break;
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programmer_delay(1);
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}
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if (error_message)
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msg_perr("%s():%d %s", function_name, lineno, error_message);
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return 1;
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}
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/* IT8502 employs a scratch ram when flash is being updated. Call the following
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* two functions before/after flash erase/program. */
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void it85xx_enter_scratch_rom()
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{
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int ret;
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int tries;
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msg_pdbg("%s():%d was called ...\n", __FUNCTION__, __LINE__);
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if (it85xx_scratch_rom_reenter > 0) return;
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it85xx_scratch_rom_reenter++;
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OUTB(0xb4, LEGACY_KBC_PORT);
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#if 0
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/* FIXME: this a workaround for the bug that SMBus signal would
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* interfere the EC firmware update. Should be removed if
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* we find out the root cause. */
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ret = system("stop powerd >&2");
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if (ret) {
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msg_perr("Cannot stop powerd.\n");
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}
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#endif
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for (tries = 0; tries < MAX_TRY; ++tries) {
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/* Wait until IBF (input buffer) is not full. */
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if (wait_for(KB_IBF, 0, MAX_TIMEOUT,
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"* timeout at waiting for IBF==0.\n",
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__FUNCTION__, __LINE__))
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continue;
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/* Copy EC firmware to SRAM. */
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OUTB(0xb4, LEGACY_KBC_PORT_CMD);
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/* Confirm EC has taken away the command. */
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if (wait_for(KB_IBF, 0, MAX_TIMEOUT,
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"* timeout at taking command.\n",
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__FUNCTION__, __LINE__))
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continue;
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/* Waiting for OBF (output buffer) has data.
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* Note sometimes the replied command might be stolen by kernel
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* ISR so that it is okay as long as the command is 0xFA. */
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if (wait_for(KB_OBF, KB_OBF, MAX_TIMEOUT, NULL, NULL, 0))
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msg_pdbg("%s():%d * timeout at waiting for OBF.\n",
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__FUNCTION__, __LINE__);
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if ((ret = INB(LEGACY_KBC_PORT_DATA)) == 0xFA) {
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break;
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} else {
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msg_perr("%s():%d * not run on SRAM ret=%d\n",
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__FUNCTION__, __LINE__, ret);
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continue;
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}
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}
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if (tries < MAX_TRY) {
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/* EC already runs on SRAM */
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it85xx_scratch_rom_reenter++;
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msg_pdbg("%s():%d * SUCCESS.\n", __FUNCTION__, __LINE__);
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} else {
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msg_perr("%s():%d * Max try reached.\n",
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__FUNCTION__, __LINE__);
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}
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}
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void it85xx_exit_scratch_rom()
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{
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#if 0
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int ret;
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#endif
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int tries;
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msg_pdbg("%s():%d was called ...\n", __FUNCTION__, __LINE__);
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if (it85xx_scratch_rom_reenter <= 0) return;
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it85xx_scratch_rom_reenter = 0;
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OUTB(0xfe, LEGACY_KBC_PORT);
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for (tries = 0; tries < MAX_TRY; ++tries) {
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/* Wait until IBF (input buffer) is not full. */
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if (wait_for(KB_IBF, 0, MAX_TIMEOUT,
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"* timeout at waiting for IBF==0.\n",
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__FUNCTION__, __LINE__))
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continue;
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/* Exit SRAM. Run on flash. */
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OUTB(0xFE, LEGACY_KBC_PORT_CMD);
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/* Confirm EC has taken away the command. */
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if (wait_for(KB_IBF, 0, MAX_TIMEOUT,
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"* timeout at taking command.\n",
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__FUNCTION__, __LINE__)) {
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/* We cannot ensure if EC has exited update mode.
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* If EC is in normal mode already, a further 0xFE
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* command will reboot system. So, exit loop here. */
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tries = MAX_TRY;
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break;
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}
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break;
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}
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if (tries < MAX_TRY) {
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it85xx_scratch_rom_reenter = 0;
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msg_pdbg("%s():%d * SUCCESS.\n", __FUNCTION__, __LINE__);
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} else {
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msg_perr("%s():%d * Max try reached.\n",
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__FUNCTION__, __LINE__);
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}
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#if 0
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/* FIXME: this a workaround for the bug that SMBus signal would
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* interfere the EC firmware update. Should be removed if
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* we find out the root cause. */
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ret = system("start powerd >&2");
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if (ret) {
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msg_perr("Cannot start powerd again.\n");
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}
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#endif
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}
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int it85xx_spi_common_init(void)
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@ -256,6 +395,14 @@ int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt,
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readarr[i] = *ce_low;
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#endif
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}
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#ifdef LPC_IO
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INDIRECT_A1(shm_io_base, (((unsigned long int)ce_high) >> 8) & 0xff);
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INDIRECT_WRITE(shm_io_base, 0xFF); /* Write anything to this address.*/
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#endif
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#ifdef LPC_MEMORY
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*ce_high = 0;
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#endif
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return 0;
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}
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@ -523,6 +523,7 @@ enum spi_controller {
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#if defined(__i386__) || defined(__x86_64__)
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SPI_CONTROLLER_ICH7,
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SPI_CONTROLLER_ICH9,
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SPI_CONTROLLER_IT85XX,
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SPI_CONTROLLER_IT87XX,
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SPI_CONTROLLER_SB600,
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SPI_CONTROLLER_VIA,
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@ -583,6 +584,14 @@ int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len
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int ich_spi_send_multicommand(struct spi_command *cmds);
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#endif
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/* it85spi.c */
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struct superio probe_superio_ite85xx(void);
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int it85xx_spi_init(void);
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int it85xx_shutdown(void);
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int it85xx_probe_spi_flash(const char *name);
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int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt,
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const unsigned char *writearr, unsigned char *readarr);
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/* it87spi.c */
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void enter_conf_mode_ite(uint16_t port);
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void exit_conf_mode_ite(uint16_t port);
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7
spi.c
7
spi.c
@ -55,6 +55,13 @@ const struct spi_programmer spi_programmer[] = {
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.write_256 = ich_spi_write_256,
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},
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{ /* SPI_CONTROLLER_IT85XX */
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.command = it85xx_spi_send_command,
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.multicommand = default_spi_send_multicommand,
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.read = ich_spi_read,
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.write_256 = ich_spi_write_256,
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},
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{ /* SPI_CONTROLLER_IT87XX */
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.command = it8716f_spi_send_command,
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.multicommand = default_spi_send_multicommand,
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