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mirror of https://review.coreboot.org/flashrom.git synced 2025-04-27 15:12:36 +02:00

spi25: Fix layering violation in default_spi_write_aai()

Change-Id: I8aa3e2992f64906edc669060936f9522d32637fb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Nico Huber 2017-04-22 00:13:15 +02:00
parent 477e1693c8
commit 504215b9f6
3 changed files with 2 additions and 16 deletions

View File

@ -115,7 +115,7 @@ static const struct spi_master spi_master_it87xx = {
.multicommand = default_spi_send_multicommand,
.read = it8716f_spi_chip_read,
.write_256 = it8716f_spi_chip_write_256,
.write_aai = default_spi_write_aai,
.write_aai = spi_chip_write_1,
};
static uint16_t it87spi_probe(uint16_t port)

14
spi25.c
View File

@ -743,20 +743,6 @@ int default_spi_write_aai(struct flashctx *flash, const uint8_t *buf, unsigned i
JEDEC_AAI_WORD_PROGRAM,
};
switch (flash->mst->spi.type) {
#if CONFIG_INTERNAL == 1
#if defined(__i386__) || defined(__x86_64__)
case SPI_CONTROLLER_IT87XX:
case SPI_CONTROLLER_WBSIO:
msg_perr("%s: impossible with this SPI controller,"
" degrading to byte program\n", __func__);
return spi_chip_write_1(flash, buf, start, len);
#endif
#endif
default:
break;
}
/* The even start address and even length requirements can be either
* honored outside this function, or we can call spi_byte_program
* for the first and/or last byte and use AAI for the rest.

View File

@ -72,7 +72,7 @@ static const struct spi_master spi_master_wbsio = {
.multicommand = default_spi_send_multicommand,
.read = wbsio_spi_read,
.write_256 = spi_chip_write_1,
.write_aai = default_spi_write_aai,
.write_aai = spi_chip_write_1,
};
int wbsio_check_for_spi(void)