openwrt/flashrom
1
0
Fork 0
mirror of https://review.coreboot.org/flashrom.git synced 2025-04-26 14:42:36 +02:00
Code Issues Releases Wiki Activity

flashchips: Add Spansion S25FS512S

Browse Source 
Tested probe, read, erase, write on FS512SAIF01 chips
using Linux SPI and DediProg SF100 programmers.

This change affects S25FL512S identification as well,
so that both chips can be unambiguously detected by probing.

Datasheets used:
* Infineon-S25FS512S_512_Mb_1-DataSheet-v16_00-EN.pdf
    at https://www.infineon.com/dgdl/?fileId=8ac78c8c7d0d8da4017d0ed681a356fe
* Infineon-S25FL512S_512_Mb_64_MB_FL-S_Flash_SPI_Multi-I_O_3-DataSheet-v21_00-EN.pdf
    at https://www.infineon.com/dgdl/?fileId=8ac78c8c7d0d8da4017d0ed046ae4b53

Change-Id: I40b6c081ec7d57eac4f6d2b69cea3878bc92bb47
Signed-off-by: Anton Samsonov <devel@zxlab.ru>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/85585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
This commit is contained in:
Anton Samsonov 2024-12-23 21:45:00 +03:00 committed by Anastasia Klimchuk
parent 2e6b0510cf
commit 52a495b443
3 changed files with 52 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

50
flashchips/spansion.c
View File

@ -935,14 +935,14 @@
.name = "S25FL512S",
.bustype = BUS_SPI,
.manufacture_id = SPANSION_ID,
.model_id = SPANSION_S25FL512,
.model_id = SPANSION_S25FL512S_UL,
.total_size = 65536, /* 512 Mb (=> 64 MB)) */
.page_size = 256,
/* OTP: 1024B total, 32B reserved; read 0x4B; write 0x42 */
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP |
FEATURE_4BA_NATIVE | FEATURE_4BA_ENTER_EAR7 | FEATURE_4BA_EAR_1716,
.tested = TEST_UNTESTED,
.probe = PROBE_SPI_RDID,
.probe = PROBE_SPI_BIG_SPANSION,
.probe_timing = TIMING_ZERO,
.block_erasers =
{
@ -1028,3 +1028,49 @@
.read = SPI_CHIP_READ,
.voltage = {1700, 2000},
},
{
.vendor = "Spansion",
.name = "S25FS512S",
.bustype = BUS_SPI,
.manufacture_id = SPANSION_ID,
.model_id = SPANSION_S25FS512S_UL,
.total_size = 65536,
.page_size = 256, /* 256 or 512 bytes page programming buffer */
/* OTP: 1024B total, 32B reserved; read 0x4B; write 0x42 */
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI |
FEATURE_4BA_NATIVE | FEATURE_4BA_ENTER,
/* Note on FEATURE_4BA_ENTER: the command set only defines command 0xB7
to enter 4BA mode, but there is no counterpart command "Exit 4BA mode",
and the code 0xE9 is assigned to another command ("Password unlock"). */
/* Note on FEATURE_4BA_ENTER_EAR7 (not set): the "Extended address mode" bit
is stored in configuration register CR2V[7], which can only be read / written
by generic commands ("Read any register" / "Write any register"), that itself
expect a 3- or 4-byte address of register in question, which in turn depends on
the same register, that is initially set from non-volatile register CR2NV[7]
that defaults to 0, but can be programmed to 1 for starting in 32-bit mode. */
.tested = TEST_OK_PREW,
.probe = PROBE_SPI_BIG_SPANSION,
.probe_timing = TIMING_ZERO,
.block_erasers =
{
{
.eraseblocks = { { 256 * 1024, 256} },
.block_erase = SPI_BLOCK_ERASE_DC,
}, {
.eraseblocks = { { 256 * 1024, 256} },
.block_erase = SPI_BLOCK_ERASE_D8,
}, {
.eraseblocks = { { 65536 * 1024, 1} },
.block_erase = SPI_BLOCK_ERASE_60,
}, {
.eraseblocks = { { 65536 * 1024, 1} },
.block_erase = SPI_BLOCK_ERASE_C7,
}
},
.printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP2_EP_SRWD, /* TODO: SR2 and many others */
.unlock = SPI_DISABLE_BLOCKPROTECT_BP2_SRWD, /* TODO: various other locks */
.write = SPI_CHIP_WRITE256,
.read = SPI_CHIP_READ,
.voltage = {1700, 2000},
},

3
include/flashchips.h
View File

@ -701,7 +701,6 @@
#define SPANSION_S25FL064A 0x0216 /* Same as S25FL064P, but the latter supports EDI and CFI */
#define SPANSION_S25FL128 0x2018 /* Same ID for various S25FL127S, S25FL128P, S25FL128S and S25FL129P (including dual-die S70FL256P) variants (EDI supported) */
#define SPANSION_S25FL256 0x0219
#define SPANSION_S25FL512 0x0220
#define SPANSION_S25FL204 0x4013
#define SPANSION_S25FL208 0x4014
#define SPANSION_S25FL216 0x4015 /* Same as S25FL216K, but the latter supports OTP, 3 status regs, quad I/O, SFDP etc. */
@ -710,6 +709,7 @@
#define SPANSION_S25FL164K 0x4017
#define SPANSION_S25FL128L 0x6018
#define SPANSION_S25FL256L 0x6019
#define SPANSION_S25FL512S_UL 0x02200080 /* Uniform Large (256kB) sectors */
#define SPANSION_S25FS128S_L 0x20180081 /* Large sectors. */
#define SPANSION_S25FS128S_S 0x20180181 /* Small sectors. */
#define SPANSION_S25FS256S_L 0x02190081 /* Large sectors. */
@ -718,6 +718,7 @@
#define SPANSION_S25FL128S_US 0x20180180 /* Uniform Small (64kB) sectors */
#define SPANSION_S25FL256S_UL 0x02190080 /* Uniform Large (128kB) sectors */
#define SPANSION_S25FL256S_US 0x02190180 /* Uniform Small (64kB) sectors */
#define SPANSION_S25FS512S_UL 0x02200081 /* Uniform Large (256kB) sectors */
/* Spansion 29GL families got a suffix indicating the process technology but share the same 3-Byte IDs. They can
* however be differentiated by CFI byte 45h. Some versions exist which have special top or bottom boot sectors

6
s25f.c
View File

@ -371,10 +371,8 @@ int probe_spi_big_spansion(struct flashctx *flash)
*
* offset value meaning
* 00h 01h Manufacturer ID for Spansion
* 01h 20h 128 Mb capacity
* 01h 02h 256 Mb capacity
* 02h 18h 128 Mb capacity
* 02h 19h 256 Mb capacity
* 01h * Memory interface type (02h, 20h, 40h, 60h)
* 02h * Memory capacity (18h = 128 Mb, 19h = 256 Mb, 20h = 512 Mb)
* 03h 4Dh Full size of the RDID output (ignored)
* 04h 00h FS: 256-kB physical sectors
* 04h 01h FS: 64-kB physical sectors