1
0
mirror of https://review.coreboot.org/flashrom.git synced 2025-08-18 21:00:15 +02:00

flashchips: Add Spansion S25FS512S

Tested probe, read, erase, write on FS512SAIF01 chips
using Linux SPI and DediProg SF100 programmers.

This change affects S25FL512S identification as well,
so that both chips can be unambiguously detected by probing.

Datasheets used:
* Infineon-S25FS512S_512_Mb_1-DataSheet-v16_00-EN.pdf
    at https://www.infineon.com/dgdl/?fileId=8ac78c8c7d0d8da4017d0ed681a356fe
* Infineon-S25FL512S_512_Mb_64_MB_FL-S_Flash_SPI_Multi-I_O_3-DataSheet-v21_00-EN.pdf
    at https://www.infineon.com/dgdl/?fileId=8ac78c8c7d0d8da4017d0ed046ae4b53

Change-Id: I40b6c081ec7d57eac4f6d2b69cea3878bc92bb47
Signed-off-by: Anton Samsonov <devel@zxlab.ru>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/85585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
This commit is contained in:
Anton Samsonov
2024-12-23 21:45:00 +03:00
committed by Anastasia Klimchuk
parent 2e6b0510cf
commit 52a495b443
3 changed files with 52 additions and 7 deletions

6
s25f.c
View File

@@ -371,10 +371,8 @@ int probe_spi_big_spansion(struct flashctx *flash)
*
* offset value meaning
* 00h 01h Manufacturer ID for Spansion
* 01h 20h 128 Mb capacity
* 01h 02h 256 Mb capacity
* 02h 18h 128 Mb capacity
* 02h 19h 256 Mb capacity
* 01h * Memory interface type (02h, 20h, 40h, 60h)
* 02h * Memory capacity (18h = 128 Mb, 19h = 256 Mb, 20h = 512 Mb)
* 03h 4Dh Full size of the RDID output (ignored)
* 04h 00h FS: 256-kB physical sectors
* 04h 01h FS: 64-kB physical sectors