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flashchips.c: remove WREN from GD25Q256D enter 4BA sequence
As noted in a comment on `commit 86fc9cf7ab221bc54ef6f10252e296fc2d7a22d2`, the GD25Q256D datasheet indicates that the chip does not require a WREN command to enter 4BA mode. Testing has confirmed that a WREN command is not required, so change the flashchip feature flags from FEATURE_4BA_WREN to FEATURE_4BA. Ticket: https://ticket.coreboot.org/issues/356 BUG=none BRANCH=none TEST=read/write/erase/verify GD25Q256D flash with FT2232H programmer TEST=called spi_enter_exit_4ba(true), dumped registers, checked ADS=1. Original-Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/70342 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Original-Reviewed-by: Nico Huber <nico.h@gmx.de> (cherry picked from commit 7f3c3f5c4807f4f3c0c2de405189e86b3f8d77a3) Change-Id: I96e48933f33c52c0d10a0d4cb7f7e07c1fceab99 Signed-off-by: Evan Benn <evanbenn@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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@ -6753,7 +6753,7 @@ const struct flashchip flashchips[] = {
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.model_id = GIGADEVICE_GD25Q256D,
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.total_size = 32768,
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.page_size = 256,
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN |
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA |
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FEATURE_WRSR_EXT2 | FEATURE_WRSR2 | FEATURE_WRSR3,
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.tested = TEST_OK_PREWB,
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.probe = PROBE_SPI_RDID,
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