mirror of
https://review.coreboot.org/flashrom.git
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ichspi: Add support for Panther Lake
This patch adds Panther Lake support into flashrom as per Intel Panther Lake SPI programming doc, number: 815466. BUG=b:347669091 TEST=Flashrom is able to detect PTL SPI DID and show chipset name as below: > flashrom --flash-name .... Found chipset "Intel Panther Lake-U/H 12Xe". .... > flashrom -p internal --ifd -i fd -i bios -r /tmp/bios.rom .... Reading ich_descriptor... done. Assuming chipset 'Panther Lake'. Using regions: "bios", "fd". Reading flash... done. SUCCESS Change-Id: I99cd8eb7cbb11381f8e8455b06cf90b9db77d8f0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83144 Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Hsuan-ting Chen <roccochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Sam McNally <sammc@google.com>
This commit is contained in:
Subrata Banik
Anastasia Klimchuk
parent
30d1b5a107
commit
57cd50cd6a
@ -607,6 +607,7 @@ static enum chipbustype enable_flash_ich_report_gcs(
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_600_SERIES_ALDER_POINT:
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case CHIPSET_METEOR_LAKE:
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case CHIPSET_PANTHER_LAKE:
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case CHIPSET_ELKHART_LAKE:
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE:
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@ -715,6 +716,7 @@ static enum chipbustype enable_flash_ich_report_gcs(
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case CHIPSET_600_SERIES_ALDER_POINT:
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case CHIPSET_C740_SERIES_EMMITSBURG:
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case CHIPSET_METEOR_LAKE:
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case CHIPSET_PANTHER_LAKE:
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boot_straps = boot_straps_pch500;
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break;
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case CHIPSET_APOLLO_LAKE:
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@ -750,6 +752,7 @@ static enum chipbustype enable_flash_ich_report_gcs(
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_600_SERIES_ALDER_POINT:
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case CHIPSET_METEOR_LAKE:
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case CHIPSET_PANTHER_LAKE:
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE:
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case CHIPSET_JASPER_LAKE:
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@ -1019,6 +1022,11 @@ static int enable_flash_mtl(const struct programmer_cfg *cfg, struct pci_dev *co
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return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_METEOR_LAKE);
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}
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static int enable_flash_ptl(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name)
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{
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return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_PANTHER_LAKE);
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}
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static int enable_flash_mcc(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name)
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{
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return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_ELKHART_LAKE);
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@ -2186,6 +2194,8 @@ const struct penable chipset_enables[] = {
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{0x8086, 0x7a8d, B_S, NT, "Intel", "WM690", enable_flash_pch600},
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{0x8086, 0x7a8c, B_S, NT, "Intel", "HM670", enable_flash_pch600},
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{0x8086, 0x7e23, B_S, DEP, "Intel", "Meteor Lake-P/M", enable_flash_mtl},
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{0x8086, 0xe323, B_S, DEP, "Intel", "Panther Lake-U/H 12Xe", enable_flash_ptl},
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{0x8086, 0xe423, B_S, DEP, "Intel", "Panther Lake-H 4Xe", enable_flash_ptl},
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#endif
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{0},
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};
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@ -50,6 +50,7 @@ ssize_t ich_number_of_regions(const enum ich_chipset cs, const struct ich_desc_c
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_600_SERIES_ALDER_POINT:
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case CHIPSET_METEOR_LAKE:
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case CHIPSET_PANTHER_LAKE:
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case CHIPSET_ELKHART_LAKE:
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case CHIPSET_JASPER_LAKE:
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return 16;
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@ -80,6 +81,7 @@ ssize_t ich_number_of_masters(const enum ich_chipset cs, const struct ich_desc_c
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_600_SERIES_ALDER_POINT:
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case CHIPSET_METEOR_LAKE:
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case CHIPSET_PANTHER_LAKE:
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case CHIPSET_GEMINI_LAKE:
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case CHIPSET_JASPER_LAKE:
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case CHIPSET_ELKHART_LAKE:
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@ -122,7 +124,7 @@ void prettyprint_ich_chipset(enum ich_chipset cs)
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"C620 series Lewisburg", "C740 series Emmitsburg", "300 series Cannon Point",
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"400 series Comet Point", "500 series Tiger Point", "600 series Alder Point",
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"Apollo Lake", "Gemini Lake", "Jasper Lake", "Elkhart Lake",
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"Meteor Lake",
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"Meteor Lake", "Panther Lake",
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};
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if (cs < CHIPSET_ICH8 || cs - CHIPSET_ICH8 + 1 >= ARRAY_SIZE(chipset_names))
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cs = 0;
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@ -220,6 +222,7 @@ static const char *pprint_density(enum ich_chipset cs, const struct ich_descript
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_600_SERIES_ALDER_POINT:
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case CHIPSET_METEOR_LAKE:
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case CHIPSET_PANTHER_LAKE:
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE:
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case CHIPSET_JASPER_LAKE:
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@ -319,6 +322,7 @@ static const char *pprint_freq(enum ich_chipset cs, uint8_t value)
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case CHIPSET_600_SERIES_ALDER_POINT:
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case CHIPSET_C740_SERIES_EMMITSBURG:
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case CHIPSET_METEOR_LAKE:
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case CHIPSET_PANTHER_LAKE:
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return freq_str[3][value];
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case CHIPSET_ELKHART_LAKE:
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return freq_str[4][value];
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@ -368,6 +372,7 @@ void prettyprint_ich_descriptor_component(enum ich_chipset cs, const struct ich_
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_600_SERIES_ALDER_POINT:
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case CHIPSET_METEOR_LAKE:
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case CHIPSET_PANTHER_LAKE:
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE:
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case CHIPSET_JASPER_LAKE:
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@ -508,7 +513,9 @@ void prettyprint_ich_descriptor_master(const enum ich_chipset cs, const struct i
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cs == CHIPSET_500_SERIES_TIGER_POINT ||
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cs == CHIPSET_600_SERIES_ALDER_POINT ||
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cs == CHIPSET_C740_SERIES_EMMITSBURG ||
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cs == CHIPSET_JASPER_LAKE || cs == CHIPSET_METEOR_LAKE) {
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cs == CHIPSET_JASPER_LAKE ||
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cs == CHIPSET_METEOR_LAKE ||
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cs == CHIPSET_PANTHER_LAKE) {
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const char *const master_names[] = {
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"BIOS", "ME", "GbE", "DevE", "EC",
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};
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@ -1083,6 +1090,8 @@ static enum ich_chipset guess_ich_chipset_from_content(const struct ich_desc_con
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return CHIPSET_JASPER_LAKE;
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else if (content->CSSO == 0x70)
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return CHIPSET_METEOR_LAKE;
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else if (content->CSSO == 0x60)
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return CHIPSET_PANTHER_LAKE;
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}
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msg_pwarn("Unknown flash descriptor, assuming 500 series compatibility.\n");
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return CHIPSET_500_SERIES_TIGER_POINT;
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@ -1107,6 +1116,7 @@ static enum ich_chipset guess_ich_chipset(const struct ich_desc_content *const c
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_600_SERIES_ALDER_POINT:
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case CHIPSET_METEOR_LAKE:
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case CHIPSET_PANTHER_LAKE:
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case CHIPSET_GEMINI_LAKE:
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case CHIPSET_JASPER_LAKE:
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case CHIPSET_ELKHART_LAKE:
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@ -1268,6 +1278,7 @@ int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_600_SERIES_ALDER_POINT:
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case CHIPSET_METEOR_LAKE:
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case CHIPSET_PANTHER_LAKE:
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE:
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case CHIPSET_JASPER_LAKE:
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@ -1314,6 +1325,7 @@ static uint32_t read_descriptor_reg(enum ich_chipset cs, uint8_t section, uint16
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_600_SERIES_ALDER_POINT:
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case CHIPSET_METEOR_LAKE:
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case CHIPSET_PANTHER_LAKE:
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE:
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case CHIPSET_JASPER_LAKE:
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10
ichspi.c
10
ichspi.c
@ -2111,6 +2111,7 @@ static void init_chipset_properties(struct swseq_data *swseq, struct hwseq_data
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case CHIPSET_JASPER_LAKE:
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case CHIPSET_ELKHART_LAKE:
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case CHIPSET_METEOR_LAKE:
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case CHIPSET_PANTHER_LAKE:
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*num_pr = 6; /* Includes GPR0 */
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*reg_pr0 = PCH100_REG_FPR0;
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swseq->reg_ssfsc = PCH100_REG_SSFSC;
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@ -2151,6 +2152,7 @@ static void init_chipset_properties(struct swseq_data *swseq, struct hwseq_data
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case CHIPSET_JASPER_LAKE:
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case CHIPSET_ELKHART_LAKE:
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case CHIPSET_METEOR_LAKE:
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case CHIPSET_PANTHER_LAKE:
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*num_freg = 16;
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break;
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default:
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@ -2213,6 +2215,7 @@ static int init_ich_default(const struct programmer_cfg *cfg, void *spibar, enum
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case CHIPSET_JASPER_LAKE:
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case CHIPSET_ELKHART_LAKE:
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case CHIPSET_METEOR_LAKE:
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case CHIPSET_PANTHER_LAKE:
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tmp = mmio_readl(spibar + PCH100_REG_DLOCK);
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msg_pdbg("0x0c: 0x%08"PRIx32" (DLOCK)\n", tmp);
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prettyprint_pch100_reg_dlock(tmp);
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@ -2294,6 +2297,7 @@ static int init_ich_default(const struct programmer_cfg *cfg, void *spibar, enum
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case CHIPSET_BAYTRAIL:
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case CHIPSET_ELKHART_LAKE:
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case CHIPSET_METEOR_LAKE:
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case CHIPSET_PANTHER_LAKE:
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break;
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default:
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ichspi_bbar = mmio_readl(spibar + ICH9_REG_BBAR);
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@ -2333,6 +2337,7 @@ static int init_ich_default(const struct programmer_cfg *cfg, void *spibar, enum
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case CHIPSET_JASPER_LAKE:
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case CHIPSET_ELKHART_LAKE:
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case CHIPSET_METEOR_LAKE:
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case CHIPSET_PANTHER_LAKE:
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break;
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default:
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tmp = mmio_readl(spibar + ICH9_REG_FPB);
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@ -2376,8 +2381,9 @@ static int init_ich_default(const struct programmer_cfg *cfg, void *spibar, enum
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ich_gen == CHIPSET_GEMINI_LAKE ||
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ich_gen == CHIPSET_JASPER_LAKE ||
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ich_gen == CHIPSET_ELKHART_LAKE ||
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ich_gen == CHIPSET_METEOR_LAKE)) {
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msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini/Jasper/Elkhart/Meteor Lake.\n");
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ich_gen == CHIPSET_METEOR_LAKE ||
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ich_gen == CHIPSET_PANTHER_LAKE)) {
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msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini/Jasper/Elkhart/Meteor/Panther Lake.\n");
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ich_spi_mode = ich_hwseq;
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}
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@ -363,6 +363,7 @@ enum ich_chipset {
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CHIPSET_ELKHART_LAKE,
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/* All chipsets after METEOR_LAKE should support checking BIOS_BM to get read/write access to of FREG0~15 */
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CHIPSET_METEOR_LAKE,
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CHIPSET_PANTHER_LAKE,
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};
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/* ichspi.c */
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