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mirror of https://review.coreboot.org/flashrom.git synced 2025-07-02 22:43:17 +02:00

ichspi: Add support for Panther Lake

This patch adds Panther Lake support into flashrom as per Intel
Panther Lake SPI programming doc, number: 815466.

BUG=b:347669091
TEST=Flashrom is able to detect PTL SPI DID and show chipset name as
below:

> flashrom --flash-name
....
Found chipset "Intel Panther Lake-U/H 12Xe".
....
> flashrom -p internal --ifd -i fd -i bios -r /tmp/bios.rom
....
Reading ich_descriptor... done.
Assuming chipset 'Panther Lake'.
Using regions: "bios", "fd".
Reading flash... done.
SUCCESS

Change-Id: I99cd8eb7cbb11381f8e8455b06cf90b9db77d8f0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83144
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
This commit is contained in:
Subrata Banik
2024-06-21 14:55:06 +00:00
committed by Anastasia Klimchuk
parent 30d1b5a107
commit 57cd50cd6a
4 changed files with 33 additions and 4 deletions

View File

@ -607,6 +607,7 @@ static enum chipbustype enable_flash_ich_report_gcs(
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_600_SERIES_ALDER_POINT:
case CHIPSET_METEOR_LAKE:
case CHIPSET_PANTHER_LAKE:
case CHIPSET_ELKHART_LAKE:
case CHIPSET_APOLLO_LAKE:
case CHIPSET_GEMINI_LAKE:
@ -715,6 +716,7 @@ static enum chipbustype enable_flash_ich_report_gcs(
case CHIPSET_600_SERIES_ALDER_POINT:
case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_METEOR_LAKE:
case CHIPSET_PANTHER_LAKE:
boot_straps = boot_straps_pch500;
break;
case CHIPSET_APOLLO_LAKE:
@ -750,6 +752,7 @@ static enum chipbustype enable_flash_ich_report_gcs(
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_600_SERIES_ALDER_POINT:
case CHIPSET_METEOR_LAKE:
case CHIPSET_PANTHER_LAKE:
case CHIPSET_APOLLO_LAKE:
case CHIPSET_GEMINI_LAKE:
case CHIPSET_JASPER_LAKE:
@ -1019,6 +1022,11 @@ static int enable_flash_mtl(const struct programmer_cfg *cfg, struct pci_dev *co
return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_METEOR_LAKE);
}
static int enable_flash_ptl(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name)
{
return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_PANTHER_LAKE);
}
static int enable_flash_mcc(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name)
{
return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_ELKHART_LAKE);
@ -2186,6 +2194,8 @@ const struct penable chipset_enables[] = {
{0x8086, 0x7a8d, B_S, NT, "Intel", "WM690", enable_flash_pch600},
{0x8086, 0x7a8c, B_S, NT, "Intel", "HM670", enable_flash_pch600},
{0x8086, 0x7e23, B_S, DEP, "Intel", "Meteor Lake-P/M", enable_flash_mtl},
{0x8086, 0xe323, B_S, DEP, "Intel", "Panther Lake-U/H 12Xe", enable_flash_ptl},
{0x8086, 0xe423, B_S, DEP, "Intel", "Panther Lake-H 4Xe", enable_flash_ptl},
#endif
{0},
};