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ichspi: Add support for Panther Lake

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This patch adds Panther Lake support into flashrom as per Intel
Panther Lake SPI programming doc, number: 815466.

BUG=b:347669091
TEST=Flashrom is able to detect PTL SPI DID and show chipset name as
below:

> flashrom --flash-name
....
Found chipset "Intel Panther Lake-U/H 12Xe".
....
> flashrom -p internal --ifd -i fd -i bios -r /tmp/bios.rom
....
Reading ich_descriptor... done.
Assuming chipset 'Panther Lake'.
Using regions: "bios", "fd".
Reading flash... done.
SUCCESS

Change-Id: I99cd8eb7cbb11381f8e8455b06cf90b9db77d8f0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83144
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
This commit is contained in:
Subrata Banik
2024-06-21 14:55:06 +00:00
committed by Anastasia Klimchuk
parent 30d1b5a107
commit 57cd50cd6a
4 changed files with 33 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
ichspi.c
View File

@@ -2111,6 +2111,7 @@ static void init_chipset_properties(struct swseq_data *swseq, struct hwseq_data
case CHIPSET_JASPER_LAKE:
case CHIPSET_ELKHART_LAKE:
case CHIPSET_METEOR_LAKE:
case CHIPSET_PANTHER_LAKE:
*num_pr = 6; /* Includes GPR0 */
*reg_pr0 = PCH100_REG_FPR0;
swseq->reg_ssfsc = PCH100_REG_SSFSC;
@@ -2151,6 +2152,7 @@ static void init_chipset_properties(struct swseq_data *swseq, struct hwseq_data
case CHIPSET_JASPER_LAKE:
case CHIPSET_ELKHART_LAKE:
case CHIPSET_METEOR_LAKE:
case CHIPSET_PANTHER_LAKE:
*num_freg = 16;
break;
default:
@@ -2213,6 +2215,7 @@ static int init_ich_default(const struct programmer_cfg *cfg, void *spibar, enum
case CHIPSET_JASPER_LAKE:
case CHIPSET_ELKHART_LAKE:
case CHIPSET_METEOR_LAKE:
case CHIPSET_PANTHER_LAKE:
tmp = mmio_readl(spibar + PCH100_REG_DLOCK);
msg_pdbg("0x0c: 0x%08"PRIx32" (DLOCK)\n", tmp);
prettyprint_pch100_reg_dlock(tmp);
@@ -2294,6 +2297,7 @@ static int init_ich_default(const struct programmer_cfg *cfg, void *spibar, enum
case CHIPSET_BAYTRAIL:
case CHIPSET_ELKHART_LAKE:
case CHIPSET_METEOR_LAKE:
case CHIPSET_PANTHER_LAKE:
break;
default:
ichspi_bbar = mmio_readl(spibar + ICH9_REG_BBAR);
@@ -2333,6 +2337,7 @@ static int init_ich_default(const struct programmer_cfg *cfg, void *spibar, enum
case CHIPSET_JASPER_LAKE:
case CHIPSET_ELKHART_LAKE:
case CHIPSET_METEOR_LAKE:
case CHIPSET_PANTHER_LAKE:
break;
default:
tmp = mmio_readl(spibar + ICH9_REG_FPB);
@@ -2376,8 +2381,9 @@ static int init_ich_default(const struct programmer_cfg *cfg, void *spibar, enum
ich_gen == CHIPSET_GEMINI_LAKE ||
ich_gen == CHIPSET_JASPER_LAKE ||
ich_gen == CHIPSET_ELKHART_LAKE ||
ich_gen == CHIPSET_METEOR_LAKE)) {
msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini/Jasper/Elkhart/Meteor Lake.\n");
ich_gen == CHIPSET_METEOR_LAKE ||
ich_gen == CHIPSET_PANTHER_LAKE)) {
msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini/Jasper/Elkhart/Meteor/Panther Lake.\n");
ich_spi_mode = ich_hwseq;
}