openwrt/flashrom
1
0
Fork 0
mirror of https://review.coreboot.org/flashrom.git synced 2025-10-16 15:21:54 +02:00
Code Issues Releases Wiki Activity

sb600spi: Check if SPI BAR register has valid value

Browse Source 
On systems where AMD ROM Armor is enabled, the SPI BAR register in
LPC PCI configuration space reads as all FFs. Check if the register
reads as all FFs and bail out early if we detect that the SPI base
address is not valid.

TEST=Flashrom does not attempt to access incorrect physical address
on Gigabyte MZ33-AR1 running vendor BIOS with ROM Armor enabled.

Change-Id: I139ea849d6147ea8e8c26ace03627b30f5297267
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/89445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
This commit is contained in:
Michał Żygowski
2025-10-07 13:36:19 +02:00
committed by Anastasia Klimchuk
parent 81e5b58a20
commit 5a4ea36b12
1 changed files with 7 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
sb600spi.c
View File

@@ -636,6 +636,13 @@ int sb600_probe_spi(const struct programmer_cfg *cfg, struct pci_dev *dev)
/* Read SPI_BaseAddr */
tmp = pci_read_long(dev, 0xa0);
/* If the BAR register is 0xffffffff, ROM Armor is likely active. */
if (tmp == UINT32_MAX) {
msg_perr("SPI BAR register is invalid.\n"
"ROM Armor is possibly active and prevents SPI access.\n");
return ERROR_FLASHROM_NONFATAL;
}
tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */
msg_pdbg("SPI base address is at 0x%"PRIx32"\n", tmp);