mirror of
https://review.coreboot.org/flashrom.git
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dummyflasher: Add a status register to SPI chips
Corresponding to flashrom svn r1532. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
This commit is contained in:
Stefan Tauner
parent
dc704edad4
commit
5e695ab4d7
@ -21,6 +21,7 @@
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#include <stdlib.h>
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#include <stdio.h>
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#include <ctype.h>
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#include <errno.h>
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#include "flash.h"
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#include "chipdrivers.h"
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#include "programmer.h"
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@ -61,6 +62,7 @@ unsigned char spi_blacklist[256];
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unsigned char spi_ignorelist[256];
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int spi_blacklist_size = 0;
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int spi_ignorelist_size = 0;
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static uint8_t emu_status = 0;
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#endif
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#endif
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@ -133,6 +135,9 @@ int dummy_init(void)
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char *bustext = NULL;
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char *tmp = NULL;
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int i;
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#if EMULATE_SPI_CHIP
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char *status = NULL;
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#endif
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#if EMULATE_CHIP
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struct stat image_stat;
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#endif
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@ -309,6 +314,23 @@ int dummy_init(void)
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return 1;
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}
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#ifdef EMULATE_SPI_CHIP
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status = extract_programmer_param("spi_status");
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if (status) {
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char *endptr;
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errno = 0;
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emu_status = strtoul(status, &endptr, 0);
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free(status);
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if (errno != 0 || status == endptr) {
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msg_perr("Error: initial status register specified, "
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"but the value could not be converted.\n");
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return 1;
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}
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msg_pdbg("Initial status register is set to 0x%02x.\n",
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emu_status);
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}
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#endif
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msg_pdbg("Filling fake flash chip with 0xff, size %i\n", emu_chip_size);
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memset(flashchip_contents, 0xff, emu_chip_size);
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@ -429,7 +451,6 @@ static int emulate_spi_chip_response(unsigned int writecnt,
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{
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unsigned int offs, i;
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static int unsigned aai_offs;
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static int aai_active = 0;
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if (writecnt == 0) {
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msg_perr("No command sent to the chip!\n");
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@ -453,6 +474,17 @@ static int emulate_spi_chip_response(unsigned int writecnt,
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return 0;
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}
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}
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if (emu_max_aai_size && (emu_status & SPI_SR_AAI)) {
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if (writearr[0] != JEDEC_AAI_WORD_PROGRAM &&
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writearr[0] != JEDEC_WRDI &&
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writearr[0] != JEDEC_RDSR) {
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msg_perr("Forbidden opcode (0x%02x) attempted during "
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"AAI sequence!\n", writearr[0]);
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return 0;
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}
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}
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switch (writearr[0]) {
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case JEDEC_RES:
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if (emu_chip != EMULATE_ST_M25P10_RES)
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@ -481,10 +513,23 @@ static int emulate_spi_chip_response(unsigned int writecnt,
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if (readcnt > 2)
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readarr[2] = 0x4a;
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break;
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case JEDEC_RDSR:
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memset(readarr, 0, readcnt);
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if (aai_active)
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memset(readarr, 1 << 6, readcnt);
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case JEDEC_RDSR: {
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memset(readarr, emu_status, readcnt);
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break;
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}
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/* FIXME: this should be chip-specific. */
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case JEDEC_EWSR:
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case JEDEC_WREN:
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emu_status |= SPI_SR_WEL;
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break;
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case JEDEC_WRSR:
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if (!(emu_status & SPI_SR_WEL)) {
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msg_perr("WRSR attempted, but WEL is 0!\n");
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break;
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}
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/* FIXME: add some reasonable simulation of the busy flag */
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emu_status = writearr[1] & ~SPI_SR_WIP;
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msg_pdbg2("WRSR wrote 0x%02x.\n", emu_status);
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break;
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case JEDEC_READ:
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offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
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@ -510,7 +555,7 @@ static int emulate_spi_chip_response(unsigned int writecnt,
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case JEDEC_AAI_WORD_PROGRAM:
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if (!emu_max_aai_size)
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break;
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if (!aai_active) {
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if (!(emu_status & SPI_SR_AAI)) {
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if (writecnt < JEDEC_AAI_WORD_PROGRAM_OUTSIZE) {
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msg_perr("Initial AAI WORD PROGRAM size too "
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"short!\n");
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@ -521,7 +566,7 @@ static int emulate_spi_chip_response(unsigned int writecnt,
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"long!\n");
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return 1;
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}
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aai_active = 1;
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emu_status |= SPI_SR_AAI;
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aai_offs = writearr[1] << 16 | writearr[2] << 8 |
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writearr[3];
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/* Truncate to emu_chip_size. */
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@ -544,9 +589,8 @@ static int emulate_spi_chip_response(unsigned int writecnt,
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}
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break;
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case JEDEC_WRDI:
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if (!emu_max_aai_size)
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break;
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aai_active = 0;
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if (emu_max_aai_size)
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emu_status &= ~SPI_SR_AAI;
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break;
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case JEDEC_SE:
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if (!emu_jedec_se_size)
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@ -633,6 +677,8 @@ static int emulate_spi_chip_response(unsigned int writecnt,
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/* No special response. */
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break;
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}
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if (writearr[0] != JEDEC_WREN && writearr[0] != JEDEC_EWSR)
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emu_status &= ~SPI_SR_WEL;
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return 0;
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}
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#endif
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@ -495,6 +495,15 @@ SPI commands. If commandlist is e.g. 0302, the emulated flash chip will ignore
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command 0x03 (READ) and command 0x02 (WRITE). commandlist may be up to 512
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characters (256 commands) long.
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Implementation note: flashrom won't detect an error during command execution.
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.sp
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.TP
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.B SPI status register
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.sp
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You can specify the initial content of the chip's status register with the
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.sp
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.B " flashrom -p dummy:spi_status=content"
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.sp
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syntax where content is an 8-bit hexadecimal value.
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.SS
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.BR "nic3com" , " nicrealtek" , " nicsmc1211" , " nicnatsemi" , " nicintel\
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" , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii\
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@ -335,7 +335,7 @@ static int it8716f_spi_page_program(struct flashctx *flash, uint8_t *buf,
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/* Wait until the Write-In-Progress bit is cleared.
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* This usually takes 1-10 ms, so wait in 1 ms steps.
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*/
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while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
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while (spi_read_status_register(flash) & SPI_SR_WIP)
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programmer_delay(1000);
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return 0;
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}
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6
spi.h
6
spi.h
@ -95,7 +95,11 @@
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#define JEDEC_RDSR 0x05
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#define JEDEC_RDSR_OUTSIZE 0x01
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#define JEDEC_RDSR_INSIZE 0x01
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#define JEDEC_RDSR_BIT_WIP (0x01 << 0)
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/* Status Register Bits */
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#define SPI_SR_WIP (0x01 << 0)
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#define SPI_SR_WEL (0x01 << 1)
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#define SPI_SR_AAI (0x01 << 6)
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/* Write Status Enable */
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#define JEDEC_EWSR 0x50
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22
spi25.c
22
spi25.c
@ -479,7 +479,7 @@ int spi_chip_erase_60(struct flashctx *flash)
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* This usually takes 1-85 s, so wait in 1 s steps.
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*/
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/* FIXME: We assume spi_read_status_register will never fail. */
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while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
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while (spi_read_status_register(flash) & SPI_SR_WIP)
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programmer_delay(1000 * 1000);
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/* FIXME: Check the status register for errors. */
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return 0;
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@ -515,7 +515,7 @@ int spi_chip_erase_c7(struct flashctx *flash)
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* This usually takes 1-85 s, so wait in 1 s steps.
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*/
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/* FIXME: We assume spi_read_status_register will never fail. */
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while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
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while (spi_read_status_register(flash) & SPI_SR_WIP)
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programmer_delay(1000 * 1000);
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/* FIXME: Check the status register for errors. */
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return 0;
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@ -557,7 +557,7 @@ int spi_block_erase_52(struct flashctx *flash, unsigned int addr,
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/* Wait until the Write-In-Progress bit is cleared.
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* This usually takes 100-4000 ms, so wait in 100 ms steps.
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*/
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while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
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while (spi_read_status_register(flash) & SPI_SR_WIP)
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programmer_delay(100 * 1000);
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/* FIXME: Check the status register for errors. */
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return 0;
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@ -604,7 +604,7 @@ int spi_block_erase_d8(struct flashctx *flash, unsigned int addr,
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/* Wait until the Write-In-Progress bit is cleared.
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* This usually takes 100-4000 ms, so wait in 100 ms steps.
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*/
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while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
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while (spi_read_status_register(flash) & SPI_SR_WIP)
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programmer_delay(100 * 1000);
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/* FIXME: Check the status register for errors. */
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return 0;
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@ -649,7 +649,7 @@ int spi_block_erase_d7(struct flashctx *flash, unsigned int addr,
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/* Wait until the Write-In-Progress bit is cleared.
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* This usually takes 100-4000 ms, so wait in 100 ms steps.
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*/
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while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
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while (spi_read_status_register(flash) & SPI_SR_WIP)
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programmer_delay(100 * 1000);
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/* FIXME: Check the status register for errors. */
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return 0;
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@ -692,7 +692,7 @@ int spi_block_erase_20(struct flashctx *flash, unsigned int addr,
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/* Wait until the Write-In-Progress bit is cleared.
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* This usually takes 15-800 ms, so wait in 10 ms steps.
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*/
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while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
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while (spi_read_status_register(flash) & SPI_SR_WIP)
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programmer_delay(10 * 1000);
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/* FIXME: Check the status register for errors. */
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return 0;
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@ -805,7 +805,7 @@ static int spi_write_status_register_flag(struct flashctx *flash, int status, co
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* 100 ms, then wait in 10 ms steps until a total of 5 s have elapsed.
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*/
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programmer_delay(100 * 1000);
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while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) {
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while (spi_read_status_register(flash) & SPI_SR_WIP) {
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if (++i > 490) {
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msg_cerr("Error: WIP bit after WRSR never cleared\n");
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return TIMEOUT_ERROR;
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@ -1035,7 +1035,7 @@ int spi_write_chunked(struct flashctx *flash, uint8_t *buf, unsigned int start,
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rc = spi_nbyte_program(flash, starthere + j, buf + starthere - start + j, towrite);
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if (rc)
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break;
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while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
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while (spi_read_status_register(flash) & SPI_SR_WIP)
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programmer_delay(10);
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}
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if (rc)
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@ -1062,7 +1062,7 @@ int spi_chip_write_1(struct flashctx *flash, uint8_t *buf, unsigned int start,
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result = spi_byte_program(flash, i, buf[i - start]);
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if (result)
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return 1;
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while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
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while (spi_read_status_register(flash) & SPI_SR_WIP)
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programmer_delay(10);
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}
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@ -1157,7 +1157,7 @@ int spi_aai_write(struct flashctx *flash, uint8_t *buf, unsigned int start,
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*/
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return result;
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}
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while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
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while (spi_read_status_register(flash) & SPI_SR_WIP)
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programmer_delay(10);
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/* We already wrote 2 bytes in the multicommand step. */
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@ -1169,7 +1169,7 @@ int spi_aai_write(struct flashctx *flash, uint8_t *buf, unsigned int start,
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cmd[2] = buf[pos++ - start];
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spi_send_command(flash, JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE, 0,
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cmd, NULL);
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while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
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while (spi_read_status_register(flash) & SPI_SR_WIP)
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programmer_delay(10);
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}
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