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chipset_enable: Add support for discrete Cannon Lake PCHs

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The Cannon Lake "300 Series" PCHs [1,2] share the register layout of the
Skylake "100 Series". Mark them as BAD until `ichspi.c` is adapted.

[1] Intel(R) 300 Series and Intel(R) C240 Series
    Chipset Family Platform Controller Hub
    Datasheet - Volume 1 of 2
    Revison 4 (Dec 2018)
    Document Number 337347

[2] Intel(R) 300 Series Chipset Families Platform Controller Hub
    Datasheet - Volume 2 of 2
    Revision 2? (Oct 2018)
    Document Number 337348

Change-Id: If0b54799d5b93169ee660409bad57ae14677340c
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jeremy Soller <jackpot51@gmail.com>
This commit is contained in:
Thomas Heijligen
2019-03-19 17:00:03 +01:00
committed by Nico Huber
parent 045b97ebd9
commit 5ec84b3c09
2 changed files with 19 additions and 0 deletions
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1
programmer.h
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@ -626,6 +626,7 @@ enum ich_chipset {
CHIPSET_9_SERIES_WILDCAT_POINT_LP,
CHIPSET_100_SERIES_SUNRISE_POINT, /* also 6th/7th gen Core i/o (LP) variants */
CHIPSET_C620_SERIES_LEWISBURG,
CHIPSET_300_SERIES_CANNON_POINT,
CHIPSET_APOLLO_LAKE,
};