openwrt/flashrom
1
0
Fork 0
mirror of https://review.coreboot.org/flashrom.git synced 2025-04-29 16:03:47 +02:00
Code Issues Releases Wiki Activity

chipset_enable.c: Mark Intel H110 as DEP

Browse Source 
Tested reading, writing and erasing the internal flash chip using an HP
280 G2 SFF mainboard with an Intel H110 PCH. However, since ME-enabled
chipsets are marked as DEP instead of OK, this one shall also be.

Change-Id: I5deac6e43a43ee9748aaa7dadae50065613488b1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/48384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This commit is contained in:
Angel Pons 2020-12-06 23:09:13 +01:00 committed by Edward O'Callaghan
parent b76d281010
commit 65067c7d8e
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
chipset_enable.c
View File

@ -2022,7 +2022,7 @@ const struct penable chipset_enables[] = {
{0x8086, 0x0284, B_S, DEP, "Intel", "Comet Lake U Premium", enable_flash_pch400},
{0x8086, 0xa141, B_S, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100},
{0x8086, 0xa142, B_S, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100},
{0x8086, 0xa143, B_S, NT, "Intel", "H110", enable_flash_pch100},
{0x8086, 0xa143, B_S, DEP, "Intel", "H110", enable_flash_pch100},
{0x8086, 0xa144, B_S, NT, "Intel", "H170", enable_flash_pch100},
{0x8086, 0xa145, B_S, NT, "Intel", "Z170", enable_flash_pch100},
{0x8086, 0xa146, B_S, NT, "Intel", "Q170", enable_flash_pch100},