mirror of
https://review.coreboot.org/flashrom.git
synced 2025-04-30 00:13:43 +02:00
Chipset/Board: vt8237: Set All mem cycles to LPC in chipset enable
Only done for VT8237R (possibly needed for VT8237 too), VT8235 does not need this (even if the original bios does so: Asus A7V8X-MX SE, MSI KT4V were verified). This then opens a floodgate of cleanups in the board enables. * EPIA SP board enable vanishes, taking EPIA CN match with it. * Asus A7V8X-MX/Tyan S2498 board enable then equals w836xx_memw_enable_2e * AOpen vKM400Am-S board enable then equals it8705_rom_write_enable * Epia M board enable becomes via_vt823x_gpio15_raise * Epia N board enable becomes via_vt823x_gpio9_raise * Asus M2V-MX board enable becomes via_vt823x_gpio5_raise * vt823x_gpio_set becomes via_vt823x_gpio_set, and now detects ISA bridge itself, in concordance with intel ich and nvidia mcp gpio. Corresponding to flashrom svn r815. Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Sean Nelson <audiohacked@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
This commit is contained in:
Luc Verhaegen
parent
db53ec5373
commit
73d2119473
215
board_enable.c
215
board_enable.c
@ -191,26 +191,41 @@ static void w836xx_memw_enable(uint16_t port)
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}
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/**
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* Common routine for several VT823x based boards.
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* Suited for:
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* - EPoX EP-8K5A2: VIA KT333 + VT8235.
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* - Albatron PM266A Pro: VIA P4M266A + VT8235.
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* - Shuttle AK31 (all versions): VIA KT266 + VT8233.
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* - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235
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* - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237.
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*/
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static void vt823x_set_all_writes_to_lpc(struct pci_dev *dev)
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static int w836xx_memw_enable_2e(const char *name)
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{
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uint8_t val;
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w836xx_memw_enable(0x2E);
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/* All memory cycles, not just ROM ones, go to LPC. */
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val = pci_read_byte(dev, 0x59);
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val &= ~0x80;
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pci_write_byte(dev, 0x59, val);
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return 0;
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}
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/**
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* VT823x: Set one of the GPIO pins.
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*/
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static void vt823x_gpio_set(struct pci_dev *dev, uint8_t gpio, int raise)
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static int via_vt823x_gpio_set(uint8_t gpio, int raise)
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{
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struct pci_dev *dev;
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uint16_t base;
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uint8_t val, bit, offset;
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dev = pci_dev_find_vendorclass(0x1106, 0x0601);
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switch (dev->device_id) {
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case 0x3177: /* VT8235 */
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case 0x3227: /* VT8237R */
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case 0x3337: /* VT8237A */
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break;
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default:
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fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n");
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return -1;
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}
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if ((gpio >= 12) && (gpio <= 15)) {
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/* GPIO12-15 -> output */
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val = pci_read_byte(dev, 0xE4);
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@ -228,7 +243,7 @@ static void vt823x_gpio_set(struct pci_dev *dev, uint8_t gpio, int raise)
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} else {
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fprintf(stderr, "\nERROR: "
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"VT823x GPIO%02d is not implemented.\n", gpio);
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return;
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return -1;
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}
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/* We need the I/O Base Address for this board's flash enable. */
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@ -243,103 +258,53 @@ static void vt823x_gpio_set(struct pci_dev *dev, uint8_t gpio, int raise)
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else
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val &= ~bit;
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OUTB(val, base + offset);
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}
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/**
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* Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs.
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*
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* We don't need to do this when using coreboot, GPIO15 is never lowered there.
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*/
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static int board_via_epia_m(const char *name)
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{
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struct pci_dev *dev;
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dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */
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if (!dev) {
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fprintf(stderr, "\nERROR: VT8235 ISA bridge not found.\n");
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return -1;
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}
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/* GPIO15 is connected to write protect. */
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vt823x_gpio_set(dev, 15, 1);
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return 0;
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}
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/**
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* Suited for:
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* - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235
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* - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237.
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* Suited for Asus M2V-MX: VIA K8M890 + VT8237A + IT8716F
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*/
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static int board_asus_a7v8x_mx(const char *name)
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static int via_vt823x_gpio5_raise(const char *name)
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{
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struct pci_dev *dev;
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dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */
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if (!dev)
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dev = pci_dev_find(0x1106, 0x3227); /* VT8237 ISA bridge */
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if (!dev) {
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fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n");
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return -1;
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}
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vt823x_set_all_writes_to_lpc(dev);
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w836xx_memw_enable(0x2E);
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return 0;
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}
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/**
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* Suited for VIAs EPIA SP and EPIA CN.
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*/
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static int board_via_epia_sp(const char *name)
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{
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struct pci_dev *dev;
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dev = pci_dev_find(0x1106, 0x3227); /* VT8237R ISA bridge */
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if (!dev) {
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fprintf(stderr, "\nERROR: VT8237R ISA bridge not found.\n");
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return -1;
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}
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vt823x_set_all_writes_to_lpc(dev);
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return 0;
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/* On M2V-MX: GPO5 is connected to WP# and TBL#. */
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return via_vt823x_gpio_set(5, 1);
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}
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/**
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* Suited for VIAs EPIA N & NL.
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*/
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static int board_via_epia_n(const char *name)
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static int via_vt823x_gpio9_raise(const char *name)
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{
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struct pci_dev *dev;
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dev = pci_dev_find(0x1106, 0x3227); /* VT8237R ISA bridge */
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if (!dev) {
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fprintf(stderr, "\nERROR: VT8237R ISA bridge not found.\n");
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return -1;
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}
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/* All memory cycles, not just ROM ones, go to LPC */
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vt823x_set_all_writes_to_lpc(dev);
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/* GPIO9 -> output */
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vt823x_gpio_set(dev, 9, 1);
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return 0;
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return via_vt823x_gpio_set(9, 1);
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}
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/**
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* Suited for:
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* - EPoX EP-8K5A2: VIA KT333 + VT8235.
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* - Albatron PM266A Pro: VIA P4M266A + VT8235.
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* - Shuttle AK31 (all versions): VIA KT266 + VT8233.
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* Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs.
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*
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* We don't need to do this for EPIA M when using coreboot, GPIO15 is never
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* lowered there.
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*/
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static int w836xx_memw_enable_2e(const char *name)
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static int via_vt823x_gpio15_raise(const char *name)
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{
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return via_vt823x_gpio_set(15, 1);
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}
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/**
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* Winbond W83697HF Super I/O + VIA VT8235 southbridge
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*
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* Suited for:
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* - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235
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* - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235
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*/
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static int board_msi_kt4v(const char *name)
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{
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int ret;
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ret = via_vt823x_gpio_set(12, 1);
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w836xx_memw_enable(0x2E);
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return 0;
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return ret;
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}
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/**
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@ -919,6 +884,7 @@ static int board_kontron_986lcd_m(const char *name)
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* Suited for:
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* - Biostar P4M80-M4: VIA P4M800 + VT8237 + IT8705AF
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* - GIGABYTE GA-7VT600: VIA KT600 + VT8237 + IT8705
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* - AOpen vKM400Am-S: VIA KM400 + VT8237 + IT8705F.
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*
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* SIS950 superio probably requires the same flash write enable.
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*/
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@ -941,49 +907,6 @@ static int it8705_rom_write_enable(const char *name)
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return 0;
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}
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/**
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* Suited for AOpen vKM400Am-S: VIA KM400 + VT8237 + IT8705F.
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*/
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static int board_aopen_vkm400(const char *name)
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{
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struct pci_dev *dev;
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dev = pci_dev_find(0x1106, 0x3227); /* VT8237 ISA bridge */
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if (!dev) {
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fprintf(stderr, "\nERROR: VT8237 ISA bridge not found.\n");
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return -1;
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}
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vt823x_set_all_writes_to_lpc(dev);
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return it8705_rom_write_enable(name);
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}
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/**
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* Winbond W83697HF Super I/O + VIA VT8235 southbridge
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*
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* Suited for:
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* - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235
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* - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235
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*/
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static int board_msi_kt4v(const char *name)
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{
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struct pci_dev *dev;
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dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */
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if (!dev) {
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fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n");
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return -1;
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}
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vt823x_set_all_writes_to_lpc(dev);
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vt823x_gpio_set(dev, 12, 1);
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w836xx_memw_enable(0x2E);
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return 0;
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}
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/**
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* Suited for Soyo SY-7VCA: Pro133A + VT82C686.
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*/
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@ -1214,26 +1137,6 @@ static int board_asus_a7v600x(const char *name)
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return it8712f_gpio_set(32, 1);
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}
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/**
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* Suited for Asus M2V-MX: VIA K8M890 + VT8237A + IT8716F
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*/
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static int board_asus_m2v_mx(const char *name)
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{
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struct pci_dev *dev;
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dev = pci_dev_find(0x1106, 0x3337); /* VT8237A ISA bridge */
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if (!dev) {
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fprintf(stderr, "\nERROR: VT8237A ISA bridge not found.\n");
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return -1;
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}
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/* GPO5 is connected to WP# and TBL#. */
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vt823x_gpio_set(dev, 5, 1);
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return 0;
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}
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/**
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* Below is the list of boards which need a special "board enable" code in
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* flashrom before their ROM chip can be accessed/written to.
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@ -1268,13 +1171,13 @@ struct board_pciid_enable board_pciid_enables[] = {
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{0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, "ASRock", "P4i65GV", intel_ich_gpio23_raise},
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{0x1022, 0x746B, 0, 0, 0, 0, 0, 0, "AGAMI", "ARUMA", "agami", "Aruma", w83627hf_gpio24_raise_2e},
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{0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, "Albatron", "PM266A", w836xx_memw_enable_2e},
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{0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, "AOpen", "vKM400Am-S", board_aopen_vkm400},
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{0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, "AOpen", "vKM400Am-S", it8705_rom_write_enable},
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{0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe61", "Artec Group", "DBE61", board_artecgroup_dbe6x},
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{0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe62", "Artec Group", "DBE62", board_artecgroup_dbe6x},
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{0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, "ASUS", "A7V600-X", board_asus_a7v600x},
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{0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, "ASUS", "A7V8X", board_asus_a7v8x},
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{0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8X-MX SE", board_asus_a7v8x_mx},
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{0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, "ASUS", "M2V-MX", board_asus_m2v_mx},
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{0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8X-MX SE", w836xx_memw_enable_2e},
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{0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, "ASUS", "M2V-MX", via_vt823x_gpio5_raise},
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{0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS", "P4B266", intel_ich_gpio22_raise},
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{0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, "ASUS", "P4B266-LM", intel_ich_gpio21_raise},
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{0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, "ASUS", "P4P800-E Deluxe", intel_ich_gpio21_raise},
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@ -1310,11 +1213,9 @@ struct board_pciid_enable board_pciid_enables[] = {
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{0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, "Shuttle", "AK38N", shuttle_ak38n},
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{0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, "Shuttle", "FN25", board_shuttle_fn25},
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{0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, "Soyo", "SY-7VCA", board_soyo_sy_7vca},
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{0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", board_asus_a7v8x_mx},
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{0x1106, 0x0314, 0x1106, 0xaa08, 0x1106, 0x3227, 0x1106, 0xAA08, NULL, NULL, "VIA", "EPIA-CN", board_via_epia_sp},
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{0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, "VIA", "EPIA M/MII/...", board_via_epia_m},
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{0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, "VIA", "EPIA-N/NL", board_via_epia_n},
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{0x1106, 0x3227, 0x1106, 0xAA01, 0x1106, 0x0259, 0x1106, 0xAA01, NULL, NULL, "VIA", "EPIA SP", board_via_epia_sp},
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{0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", w836xx_memw_enable_2e},
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{0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, "VIA", "EPIA M/MII/...", via_vt823x_gpio15_raise},
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{0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, "VIA", "EPIA-N/NL", via_vt823x_gpio9_raise},
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{0x1106, 0x5337, 0x1458, 0xb003, 0x1106, 0x287e, 0x1106, 0x337e, NULL, NULL, "VIA", "PC3500G", it87xx_probe_spi_flash},
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{ 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL}, /* end marker */
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@ -667,6 +667,13 @@ static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
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return -1;
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}
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if (dev->device_id == 0x3227) { /* VT8237R */
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/* All memory cycles, not just ROM ones, go to LPC. */
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val = pci_read_byte(dev, 0x59);
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val &= ~0x80;
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pci_write_byte(dev, 0x59, val);
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}
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return 0;
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}
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2
print.c
2
print.c
@ -346,10 +346,12 @@ const struct board_info boards_ok[] = {
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{ "Tyan", "S5376G2NR/S5376WAG2NR", },
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{ "Tyan", "S5377", },
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{ "Tyan", "S5397", },
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{ "VIA", "EPIA-CN", },
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{ "VIA", "EPIA-EX15000G", },
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{ "VIA", "EPIA-LN", },
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{ "VIA", "EPIA-M700", },
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{ "VIA", "EPIA-NX15000G", },
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{ "VIA", "EPIA-SP", },
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{ "VIA", "NAB74X0", },
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{ "VIA", "pc2500e", },
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{ "VIA", "VB700X", },
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Block a user