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ichspi: Call Set Flash Address API from Read/Write Status functions

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This patch calls into `ich_hwseq_set_addr` function by passing
flash address `0` while performing Read and Write status operation
as Intel SPI BWG recommends that "SW should program the FADDR every
time before any transaction as FADDR is used to determine which Chip Select, CS0 if FADDR <= device 0 size, else CS1".

The reason behind setting the flash address in this patch is to adhere
to the Intel recommended reference implementation that programs FADDR.

Additionally, the followup patch will factor out `hwseq_xfer` logic
to create a helper function that ensures all SPI related operational
APIs could leverage the common `hwseq_xfer` logic.

BUG=b:223630977
TEST=Able to perform read-status/write-status operation on PCH
600 series chipset (board name: google/kano).

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib1d85ebdde99a31728f404d66a1eb4e3599b9054
Reviewed-on: https://review.coreboot.org/c/flashrom/+/65468
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2022-06-28 11:49:10 +05:30 committed by Edward O'Callaghan
parent edcea80d68
commit 7b82b51630
1 changed files with 2 additions and 0 deletions
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2
ichspi.c
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@ -1348,6 +1348,7 @@ static int ich_hwseq_read_status(const struct flashctx *flash, enum flash_reg re
return -1;
}
msg_pdbg("Reading Status register\n");
ich_hwseq_set_addr(0);
/* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
@ -1383,6 +1384,7 @@ static int ich_hwseq_write_status(const struct flashctx *flash, enum flash_reg r
return -1;
}
msg_pdbg("Writing status register\n");
ich_hwseq_set_addr(0);
/* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));