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chipset_enable.c: add PCI ID for TGL-UP3

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Add PCI ID for the Tiger Lake UP3 (Industrial SKU) SoC.

Change-Id: Ie93af14eb5857bfe51964f6565e475b6249dd407
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/70388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
This commit is contained in:
Jan Samek 2022-12-06 16:42:56 +01:00 committed by Anastasia Klimchuk
parent 58888f78f3
commit 7cab790a46
1 changed files with 1 additions and 0 deletions
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chipset_enable.c
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@ -2080,6 +2080,7 @@ const struct penable chipset_enables[] = {
{0x8086, 0x0284, B_S, DEP, "Intel", "Comet Lake U Premium", enable_flash_pch400},
{0x8086, 0x0285, B_S, DEP, "Intel", "Comet Lake U Base", enable_flash_pch400},
{0x8086, 0xa082, B_S, DEP, "Intel", "Tiger Lake U Premium", enable_flash_pch500},
{0x8086, 0xa088, B_S, DEP, "Intel", "Tiger Lake UP3", enable_flash_pch500},
{0x8086, 0xa141, B_S, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100},
{0x8086, 0xa142, B_S, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100},
{0x8086, 0xa143, B_S, DEP, "Intel", "H110", enable_flash_pch100},