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Various nicrealtek fixes
- Add missing entries for 'flashrom -L' output and wiki output. - Add missing entries in the manpage. - nicrealtek.c: Coding style fixes and cosmetics. Corresponding to flashrom svn r1011. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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@ -152,6 +152,10 @@ Specify the programmer device. Currently supported are:
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.sp
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.BR "* nic3com" " (for flash ROMs on 3COM network cards)"
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.sp
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.BR "* nicrealtek" " (for flash ROMs on Realtek network cards)"
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.sp
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.BR "* nicsmc1211" " (for flash ROMs on RTL8139-compatible SMC2 network cards)"
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.sp
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.BR "* gfxnvidia" " (for flash ROMs on NVIDIA graphics cards)"
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.sp
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.BR "* drkaiser" " (for flash ROMs on Dr. Kaiser PC-Waechter PCI cards)"
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@ -276,7 +280,7 @@ in any order.
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Example:
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.B "flashrom -p dummy:lpc,fwh"
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.TP
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.BR "nic3com" , " gfxnvidia" , " satasii " and " atahpt " programmers
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.BR "nic3com" , " nicrealtek" , " nicsmc1211" , " gfxnvidia" , " satasii " and " atahpt " programmers
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These programmers have an option to specify the PCI address of the card
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your want to use, which must be specified if more than one card supported
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by the selected programmer is installed in your system. The syntax is
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40
nicrealtek.c
40
nicrealtek.c
@ -30,34 +30,34 @@
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#define BIOS_ROM_DATA 0xD7
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struct pcidev_status nics_realtek[] = {
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{0x10ec, 0x8139, OK, "Realtek","rtl8139b/c PCI 10/100 Mbps"},
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{0x10ec, 0x8139, OK, "Realtek", "RTL8139/8139C/8139C+"},
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{},
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};
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struct pcidev_status nics_realteksmc1211[] = {
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{0x1113, 0x1211, OK, "SMC", "SMC 1211TX rtl8139 clone 10/100 Mbps"},
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{}
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{0x1113, 0x1211, OK, "SMC2", "1211TX"}, /* RTL8139 clone */
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{},
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};
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int nicrealtek_init(void)
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{
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get_io_perms();
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io_base_addr = pcidev_init(PCI_VENDOR_ID_REALTEK, PCI_BASE_ADDRESS_0,
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nics_realtek, programmer_param);
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nics_realtek, programmer_param);
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buses_supported = CHIP_BUSTYPE_PARALLEL;
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return 0;
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}
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int nicsmc1211_init(void)
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{
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get_io_perms();
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io_base_addr = pcidev_init(PCI_VENDOR_ID_SMC1211, PCI_BASE_ADDRESS_0,
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nics_realteksmc1211, programmer_param);
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nics_realteksmc1211, programmer_param);
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buses_supported = CHIP_BUSTYPE_PARALLEL;
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return 0;
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@ -73,17 +73,23 @@ int nicrealtek_shutdown(void)
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void nicrealtek_chip_writeb(uint8_t val, chipaddr addr)
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{
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OUTL(((uint32_t)addr &0x01FFFF)|0x0A0000| (val << 24), io_base_addr + BIOS_ROM_ADDR);
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OUTL(((uint32_t)addr &0x01FFFF)|0x1E0000| (val << 24), io_base_addr + BIOS_ROM_ADDR);
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OUTL(((uint32_t)addr & 0x01FFFF) | 0x0A0000 | (val << 24),
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io_base_addr + BIOS_ROM_ADDR);
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OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
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io_base_addr + BIOS_ROM_ADDR);
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}
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uint8_t nicrealtek_chip_readb(const chipaddr addr)
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{
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uint8_t val=INB(io_base_addr + BIOS_ROM_DATA);
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OUTL(((uint32_t)addr & 0x01FFFF) | 0x060000 | (val << 24), io_base_addr + BIOS_ROM_ADDR);
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val=INB(io_base_addr + BIOS_ROM_DATA);
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OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24), io_base_addr + BIOS_ROM_ADDR);
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return val ;
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uint8_t val;
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val = INB(io_base_addr + BIOS_ROM_DATA);
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OUTL(((uint32_t)addr & 0x01FFFF) | 0x060000 | (val << 24),
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io_base_addr + BIOS_ROM_ADDR);
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val = INB(io_base_addr + BIOS_ROM_DATA);
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OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
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io_base_addr + BIOS_ROM_ADDR);
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return val;
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}
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4
print.c
4
print.c
@ -238,6 +238,10 @@ void print_supported(void)
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#if NIC3COM_SUPPORT == 1
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print_supported_pcidevs(nics_3com);
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#endif
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#if NICREALTEK_SUPPORT == 1
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print_supported_pcidevs(nics_realtek);
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print_supported_pcidevs(nics_realteksmc1211);
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#endif
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#if GFXNVIDIA_SUPPORT == 1
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print_supported_pcidevs(gfx_nvidia);
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#endif
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@ -592,6 +592,10 @@ void print_supported_wiki(void)
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#if NIC3COM_SUPPORT == 1
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print_supported_pcidevs_wiki(nics_3com);
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#endif
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#if NICREALTEK_SUPPORT == 1
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print_supported_pcidevs_wiki(nics_realtek);
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print_supported_pcidevs_wiki(nics_realteksmc1211);
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#endif
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#if GFXNVIDIA_SUPPORT == 1
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print_supported_pcidevs_wiki(gfx_nvidia);
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#endif
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