1
0
mirror of https://review.coreboot.org/flashrom.git synced 2025-04-27 07:02:34 +02:00

it87spi.c: Allow passing programmer_cfg directly

Modify the type signature of the programmer entry-point
xxx_init() functions to allow for the consumption of the
programmer parameterisation string data.

Change-Id: I598b1811c9734f41eee205d5a2b51ad8ac79e3ab
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/66662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
This commit is contained in:
Edward O'Callaghan 2022-08-12 14:13:01 +10:00 committed by Anastasia Klimchuk
parent 1233e63833
commit 848825e049
3 changed files with 5 additions and 5 deletions

View File

@ -372,7 +372,7 @@ int amd_imc_shutdown(struct pci_dev *dev);
void enter_conf_mode_ite(uint16_t port);
void exit_conf_mode_ite(uint16_t port);
void probe_superio_ite(void);
int init_superio_ite(void);
int init_superio_ite(const struct programmer_cfg *cfg);
#if CONFIG_LINUX_MTD == 1
/* trivial wrapper to avoid cluttering internal_init() with #if */

View File

@ -293,7 +293,7 @@ static int internal_init(const struct programmer_cfg *cfg)
#if defined(__i386__) || defined(__x86_64__)
/* Probe unconditionally for ITE Super I/O chips. This enables LPC->SPI translation on IT87* and
* parallel writes on IT8705F. Also, this handles the manual chip select for Gigabyte's DualBIOS. */
init_superio_ite();
init_superio_ite(cfg);
if (board_flash_enable(board_vendor, board_model, cb_vendor, cb_model)) {
msg_perr("Aborting to be safe.\n");

View File

@ -321,7 +321,7 @@ static const struct spi_master spi_master_it87xx = {
.probe_opcode = default_spi_probe_opcode,
};
static uint16_t it87spi_probe(uint16_t port)
static uint16_t it87spi_probe(const struct programmer_cfg *cfg, uint16_t port)
{
uint8_t tmp = 0;
uint16_t flashport = 0;
@ -440,7 +440,7 @@ static uint16_t it87spi_probe(uint16_t port)
return register_spi_master(&spi_master_it87xx, data);
}
int init_superio_ite(void)
int init_superio_ite(const struct programmer_cfg *cfg)
{
int i;
int ret = 0;
@ -458,7 +458,7 @@ int init_superio_ite(void)
case 0x8718:
case 0x8720:
case 0x8728:
ret |= it87spi_probe(superios[i].port);
ret |= it87spi_probe(cfg, superios[i].port);
break;
default:
msg_pdbg2("Super I/O ID 0x%04hx is not on the list of flash-capable controllers.\n",