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it87spi.c: Allow passing programmer_cfg directly
Modify the type signature of the programmer entry-point xxx_init() functions to allow for the consumption of the programmer parameterisation string data. Change-Id: I598b1811c9734f41eee205d5a2b51ad8ac79e3ab Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
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@ -372,7 +372,7 @@ int amd_imc_shutdown(struct pci_dev *dev);
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void enter_conf_mode_ite(uint16_t port);
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void enter_conf_mode_ite(uint16_t port);
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void exit_conf_mode_ite(uint16_t port);
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void exit_conf_mode_ite(uint16_t port);
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void probe_superio_ite(void);
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void probe_superio_ite(void);
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int init_superio_ite(void);
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int init_superio_ite(const struct programmer_cfg *cfg);
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#if CONFIG_LINUX_MTD == 1
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#if CONFIG_LINUX_MTD == 1
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/* trivial wrapper to avoid cluttering internal_init() with #if */
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/* trivial wrapper to avoid cluttering internal_init() with #if */
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@ -293,7 +293,7 @@ static int internal_init(const struct programmer_cfg *cfg)
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#if defined(__i386__) || defined(__x86_64__)
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#if defined(__i386__) || defined(__x86_64__)
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/* Probe unconditionally for ITE Super I/O chips. This enables LPC->SPI translation on IT87* and
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/* Probe unconditionally for ITE Super I/O chips. This enables LPC->SPI translation on IT87* and
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* parallel writes on IT8705F. Also, this handles the manual chip select for Gigabyte's DualBIOS. */
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* parallel writes on IT8705F. Also, this handles the manual chip select for Gigabyte's DualBIOS. */
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init_superio_ite();
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init_superio_ite(cfg);
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if (board_flash_enable(board_vendor, board_model, cb_vendor, cb_model)) {
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if (board_flash_enable(board_vendor, board_model, cb_vendor, cb_model)) {
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msg_perr("Aborting to be safe.\n");
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msg_perr("Aborting to be safe.\n");
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@ -321,7 +321,7 @@ static const struct spi_master spi_master_it87xx = {
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.probe_opcode = default_spi_probe_opcode,
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.probe_opcode = default_spi_probe_opcode,
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};
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};
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static uint16_t it87spi_probe(uint16_t port)
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static uint16_t it87spi_probe(const struct programmer_cfg *cfg, uint16_t port)
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{
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{
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uint8_t tmp = 0;
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uint8_t tmp = 0;
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uint16_t flashport = 0;
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uint16_t flashport = 0;
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@ -440,7 +440,7 @@ static uint16_t it87spi_probe(uint16_t port)
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return register_spi_master(&spi_master_it87xx, data);
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return register_spi_master(&spi_master_it87xx, data);
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}
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}
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int init_superio_ite(void)
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int init_superio_ite(const struct programmer_cfg *cfg)
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{
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{
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int i;
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int i;
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int ret = 0;
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int ret = 0;
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@ -458,7 +458,7 @@ int init_superio_ite(void)
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case 0x8718:
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case 0x8718:
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case 0x8720:
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case 0x8720:
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case 0x8728:
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case 0x8728:
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ret |= it87spi_probe(superios[i].port);
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ret |= it87spi_probe(cfg, superios[i].port);
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break;
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break;
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default:
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default:
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msg_pdbg2("Super I/O ID 0x%04hx is not on the list of flash-capable controllers.\n",
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msg_pdbg2("Super I/O ID 0x%04hx is not on the list of flash-capable controllers.\n",
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