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flashchips.c: Add GD25Q256D from downstream
Take definition of GD25Q256D from ChromiumOS repository. This chip was added in `commit 0c38355c` by dlaurie@google.com 2019-03-17. Signed-off-by: Alan Green <avg@google.com> Change-Id: I79d4ed48aa9126a8a6ce455a9564451346195b8f Reviewed-on: https://review.coreboot.org/c/flashrom/+/35480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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flashchips.c
38
flashchips.c
@ -6274,6 +6274,44 @@ const struct flashchip flashchips[] = {
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.voltage = {2700, 3600},
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},
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{
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.vendor = "GigaDevice",
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.name = "GD25Q256D",
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.bustype = BUS_SPI,
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.manufacture_id = GIGADEVICE_ID,
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.model_id = GIGADEVICE_GD25Q256D,
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.total_size = 32768,
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.page_size = 256,
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN,
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.tested = TEST_UNTESTED,
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.probe = probe_spi_rdid,
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.probe_timing = TIMING_ZERO,
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.block_erasers =
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{
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{
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.eraseblocks = { {4 * 1024, 8192} },
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.block_erase = spi_block_erase_20,
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}, {
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.eraseblocks = { {32 * 1024, 1024} },
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.block_erase = spi_block_erase_52,
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}, {
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.eraseblocks = { {64 * 1024, 512} },
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.block_erase = spi_block_erase_d8,
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}, {
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.eraseblocks = { {32 * 1024 * 1024, 1} },
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.block_erase = spi_block_erase_60,
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}, {
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.eraseblocks = { {32 * 1024 * 1024, 1} },
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.block_erase = spi_block_erase_c7,
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}
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},
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.printlock = spi_prettyprint_status_register_bp3_srwd,
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.unlock = spi_disable_blockprotect,
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.write = spi_chip_write_256,
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.read = spi_chip_read,
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.voltage = {2700, 3600},
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},
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{
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.vendor = "GigaDevice",
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.name = "GD25Q32(B)",
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@ -372,6 +372,7 @@
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#define GIGADEVICE_GD25Q32 0x4016 /* Same as GD25Q32B */
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#define GIGADEVICE_GD25Q64 0x4017 /* Same as GD25Q64B */
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#define GIGADEVICE_GD25Q128 0x4018 /* GD25Q128B and GD25Q128C only, can be distinguished by SFDP */
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#define GIGADEVICE_GD25Q256D 0x4019
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#define GIGADEVICE_GD25VQ21B 0x4212
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#define GIGADEVICE_GD25VQ41B 0x4213 /* Same as GD25VQ40C, can be distinguished by SFDP */
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#define GIGADEVICE_GD25VQ80C 0x4214
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