openwrt/flashrom
1
0
Fork 0
mirror of https://review.coreboot.org/flashrom.git synced 2025-04-26 14:42:36 +02:00
Code Issues Releases Wiki Activity

Enable fwh_idsel parameter for C-ICH and ICH2/3/4/5 chipsets

Browse Source 
Register locations are different from ICH6, but otherwise appear
to have identical bit specifications and defaults.

Corresponding to flashrom svn r1748.

Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
This commit is contained in:
Kyösti Mälkki 2013-09-14 23:37:01 +00:00 committed by Stefan Tauner
parent 78cd0875a2
commit 88ee040ab9
2 changed files with 23 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
chipset_enable.c
View File

@ -323,7 +323,7 @@ static int enable_flash_ich0(struct pci_dev *dev, const char *name)
return enable_flash_ich(dev, name, 0x4e);
}
static int enable_flash_ich_fwh_decode(struct pci_dev *dev, const char *name)
static int enable_flash_ich_fwh_decode(struct pci_dev *dev, const char *name, enum ich_chipset ich_generation)
{
uint32_t fwh_conf;
uint8_t fwh_sel1, fwh_sel2, fwh_dec_en_lo, fwh_dec_en_hi;
@ -332,11 +332,20 @@ static int enable_flash_ich_fwh_decode(struct pci_dev *dev, const char *name)
int max_decode_fwh_idsel = 0, max_decode_fwh_decode = 0;
int contiguous = 1;
/* Register map from ICH6 onwards. */
fwh_sel1 = 0xd0;
fwh_sel2 = 0xd4;
fwh_dec_en_lo = 0xd8;
fwh_dec_en_hi = 0xd9;
if (ich_generation >= CHIPSET_ICH6) {
fwh_sel1 = 0xd0;
fwh_sel2 = 0xd4;
fwh_dec_en_lo = 0xd8;
fwh_dec_en_hi = 0xd9;
} else if (ich_generation >= CHIPSET_ICH2) {
fwh_sel1 = 0xe8;
fwh_sel2 = 0xee;
fwh_dec_en_lo = 0xf0;
fwh_dec_en_hi = 0xe3;
} else {
msg_perr("Error: FWH decode setting not implemented.\n");
return ERROR_FATAL;
}
idsel = extract_programmer_param("fwh_idsel");
if (idsel && strlen(idsel)) {
@ -441,11 +450,12 @@ idsel_garbage_out:
static int enable_flash_ich_4e(struct pci_dev *dev, const char *name, enum ich_chipset ich_generation)
{
/*
* Note: ICH5 has registers similar to FWH_SEL1, FWH_SEL2 and
* FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and
* FB_DEC_EN2.
*/
int err;
/* Configure FWH IDSEL decoder maps. */
if ((err = enable_flash_ich_fwh_decode(dev, name, ich_generation)) != 0)
return err;
internal_buses_supported = BUS_FWH;
return enable_flash_ich(dev, name, 0x4e);
}
@ -475,7 +485,7 @@ static int enable_flash_ich_dc(struct pci_dev *dev, const char *name, enum ich_c
int err;
/* Configure FWH IDSEL decoder maps. */
if ((err = enable_flash_ich_fwh_decode(dev, name)) != 0)
if ((err = enable_flash_ich_fwh_decode(dev, name, ich_generation)) != 0)
return err;
/* If we're called by enable_flash_ich_dc_spi, it will override

2
flashrom.8.tmpl
View File

@ -397,7 +397,7 @@ syntax. If this leads to erase or write accesses to the flash it would most
probably bring it into an inconsistent and unbootable state and we will not
provide any support in such a case.
.sp
If you have an Intel chipset with an ICH6 or later southbridge and if you want
If you have an Intel chipset with an ICH2 or later southbridge and if you want
to set specific IDSEL values for a non-default flash chip or an embedded
controller (EC), you can use the
.sp