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Code Issues Releases Wiki Activity

Add additional error handling to pcidev_readbar() callers

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This is mostly a leftover of Niklas' "remove exit call from pcidev_init" patch.
While not explicitly necessary detecting errors early is usually a good idea.

Corresponding to flashrom svn r1718.

Signed-off-by: Niklas Söderlund <niso@kth.se>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
This commit is contained in:
Niklas Söderlund 2013-08-23 23:29:23 +00:00 committed by Stefan Tauner
parent 184c52c941
commit 89edf36c17
12 changed files with 36 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
atahpt.c
View File

@ -69,6 +69,8 @@ int atahpt_init(void)
return 1;
io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_4);
if (!io_base_addr)
return 1;
/* Enable flash access. */
reg32 = pci_read_long(dev, REG_FLASH_ACCESS);

2
drkaiser.c
View File

@ -69,6 +69,8 @@ int drkaiser_init(void)
return 1;
addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_2);
if (!addr)
return 1;
/* Write magic register to enable flash write. */
rpci_write_word(dev, PCI_MAGIC_DRKAISER_ADDR, PCI_MAGIC_DRKAISER_VALUE);

3
gfxnvidia.c
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@ -90,6 +90,9 @@ int gfxnvidia_init(void)
return 1;
io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
if (!io_base_addr)
return 1;
io_base_addr += 0x300000;
msg_pinfo("Detected NVIDIA I/O base address: 0x%x.\n", io_base_addr);

2
nic3com.c
View File

@ -96,6 +96,8 @@ int nic3com_init(void)
return 1;
io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
if (!io_base_addr)
return 1;
id = dev->device_id;

7
nicintel.c
View File

@ -76,12 +76,17 @@ int nicintel_init(void)
return 1;
addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_2);
if (!addr)
return 1;
nicintel_bar = rphysmap("Intel NIC flash", addr, NICINTEL_MEMMAP_SIZE);
if (nicintel_bar == ERROR_PTR)
return 1;
addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
/* FIXME: This is not an aligned mapping. Use 4k? */
if (!addr)
return 1;
nicintel_control_bar = rphysmap("Intel NIC control/status reg", addr, NICINTEL_CONTROL_MEMMAP_SIZE);
if (nicintel_control_bar == ERROR_PTR)
return 1;

3
nicintel_spi.c
View File

@ -173,6 +173,9 @@ int nicintel_spi_init(void)
return 1;
io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
if (!io_base_addr)
return 1;
nicintel_spibar = rphysmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, MEMMAP_SIZE);
/* Automatic restore of EECD on shutdown is not possible because EECD
* does not only contain FLASH_WRITES_DISABLED|FLASH_WRITES_ENABLED,

2
nicnatsemi.c
View File

@ -64,6 +64,8 @@ int nicnatsemi_init(void)
return 1;
io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
if (!io_base_addr)
return 1;
/* The datasheet shows address lines MA0-MA16 in one place and MA0-MA15
* in another. My NIC has MA16 connected to A16 on the boot ROM socket

2
nicrealtek.c
View File

@ -69,6 +69,8 @@ int nicrealtek_init(void)
return 1;
io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
if (!io_base_addr)
return 1;
/* Beware, this ignores the vendor ID! */
switch (dev->device_id) {

3
ogp_spi.c
View File

@ -131,6 +131,9 @@ int ogp_spi_init(void)
return 1;
io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
if (!io_base_addr)
return 1;
ogp_spibar = rphysmap("OGP registers", io_base_addr, 4096);
if (ogp_spibar == ERROR_PTR)
return 1;

2
pcidev.c
View File

@ -94,7 +94,7 @@ uintptr_t pcidev_readbar(struct pci_dev *dev, int bar)
supported_cycles = pci_read_word(dev, PCI_COMMAND);
msg_pdbg("Requested BAR is ");
msg_pdbg("Requested BAR is of type ");
switch (bartype) {
case TYPE_MEMBAR:
msg_pdbg("MEM");

6
satamv.c
View File

@ -88,6 +88,9 @@ int satamv_init(void)
return 1;
addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
if (!addr)
return 1;
mv_bar = rphysmap("Marvell 88SX7042 registers", addr, 0x20000);
if (mv_bar == ERROR_PTR)
return 1;
@ -136,6 +139,9 @@ int satamv_init(void)
/* Get I/O BAR location. */
tmp = pcidev_readbar(dev, PCI_BASE_ADDRESS_2);
if (!addr)
return 1;
/* Truncate to reachable range.
* FIXME: Check if the I/O BAR is actually reachable.
* This is an arch specific check.

4
satasii.c
View File

@ -85,9 +85,13 @@ int satasii_init(void)
if ((id == 0x3132) || (id == 0x3124)) {
addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
if (!addr)
return 1;
reg_offset = 0x70;
} else {
addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_5);
if (!addr)
return 1;
reg_offset = 0x50;
}