openwrt/flashrom
1
0
Fork 0
mirror of https://review.coreboot.org/flashrom.git synced 2025-04-26 22:52:34 +02:00
Code Issues Releases Wiki Activity

chipset_enable.c: Mark Intel B150 and Q170 as tested

Browse Source 
Mark both B150 and Q170 as tested (DEP, as writability depends on the
flash descriptor). B150 was found in a ThinkCentre M700 Tiny, and Q170
in a ThinkCentre M900 Tiny, both support internal flashing once coreboot
is flashed (and coreboot SPI flash lockdown is not enabled).

Change-Id: Iedf4c77e3228628ac1a8726c1a9b4fb733d63d40
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/87045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
This commit is contained in:
Michał Kopeć 2025-03-29 20:53:01 +01:00 committed by Anastasia Klimchuk
parent 0cad6dfd68
commit 90cc93d9bb
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
chipset_enable.c
View File

@ -2115,9 +2115,9 @@ const struct penable chipset_enables[] = {
{0x8086, 0xa143, B_S, DEP, "Intel", "H110", enable_flash_pch100},
{0x8086, 0xa144, B_S, NT, "Intel", "H170", enable_flash_pch100},
{0x8086, 0xa145, B_S, NT, "Intel", "Z170", enable_flash_pch100},
{0x8086, 0xa146, B_S, NT, "Intel", "Q170", enable_flash_pch100},
{0x8086, 0xa146, B_S, DEP, "Intel", "Q170", enable_flash_pch100},
{0x8086, 0xa147, B_S, NT, "Intel", "Q150", enable_flash_pch100},
{0x8086, 0xa148, B_S, NT, "Intel", "B150", enable_flash_pch100},
{0x8086, 0xa148, B_S, DEP, "Intel", "B150", enable_flash_pch100},
{0x8086, 0xa149, B_S, NT, "Intel", "C236", enable_flash_pch100},
{0x8086, 0xa14a, B_S, NT, "Intel", "C232", enable_flash_pch100},
{0x8086, 0xa14b, B_S, NT, "Intel", "Sunrise Point Server Sample", enable_flash_pch100},