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Add Tiger Lake U Premium support
Tiger Lake has very low ICCRIBA (TGL=0x11, CNL=0x34 and CML=0x34) and detects as unknown chipset compatible with 300 series chipset. Add a new enum CHIPSET_500_SERIES_TIGER_POINT and treat it identically to CHIPSET_400_SERIES_COMET_POINT. There are some exceptions though, ICCRIBA is no longer present n descriptor content so a new union has been defined for new fields and used in descriptor guessing. freq_read field is not present on Tiger Lake, moreover in CannonPoint and Comet Point this field is used as eSPI/EC frequency, so a new function to print read frequency has ben added. Finally Tiger lake boot straps include eSPI, so a new bus has been added for the new straps. TEST=Flash BIOS region on Intel i5-1135G7 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I28f3b6fe9f8ce9e976a6808683f46b6f4ec72bdd Reviewed-on: https://review.coreboot.org/c/flashrom/+/55578 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michał Żygowski
committed by
Nico Huber
Nico Huber
parent
5020cf3a62
commit
93b01904db
@ -600,6 +600,7 @@ static enum chipbustype enable_flash_ich_report_gcs(
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case CHIPSET_C620_SERIES_LEWISBURG:
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case CHIPSET_300_SERIES_CANNON_POINT:
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case CHIPSET_400_SERIES_COMET_POINT:
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE:
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reg_name = "BIOS_SPI_BC";
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@ -653,6 +654,9 @@ static enum chipbustype enable_flash_ich_report_gcs(
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static const struct boot_straps boot_straps_pch8_lp[] =
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{ { "SPI", BUS_SPI },
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{ "LPC", BUS_LPC | BUS_FWH } };
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static const struct boot_straps boot_straps_pch500[] =
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{ { "SPI", BUS_SPI },
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{ "eSPI", BUS_NONE } };
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static const struct boot_straps boot_straps_apl[] =
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{ { "SPI", BUS_SPI },
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{ "reserved", BUS_NONE } };
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@ -699,6 +703,9 @@ static enum chipbustype enable_flash_ich_report_gcs(
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case CHIPSET_400_SERIES_COMET_POINT:
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boot_straps = boot_straps_pch8_lp;
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break;
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case CHIPSET_500_SERIES_TIGER_POINT:
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boot_straps = boot_straps_pch500;
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break;
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE:
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boot_straps = boot_straps_apl;
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@ -727,6 +734,7 @@ static enum chipbustype enable_flash_ich_report_gcs(
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case CHIPSET_C620_SERIES_LEWISBURG:
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case CHIPSET_300_SERIES_CANNON_POINT:
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case CHIPSET_400_SERIES_COMET_POINT:
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE:
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bbs = (gcs >> 6) & 0x1;
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@ -974,6 +982,11 @@ static int enable_flash_pch400(struct pci_dev *const dev, const char *const name
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return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_400_SERIES_COMET_POINT);
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}
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static int enable_flash_pch500(struct pci_dev *const dev, const char *const name)
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{
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return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_500_SERIES_TIGER_POINT);
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}
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static int enable_flash_apl(struct pci_dev *const dev, const char *const name)
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{
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return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE);
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@ -2029,6 +2042,7 @@ const struct penable chipset_enables[] = {
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{0x8086, 0x9d84, B_S, DEP, "Intel", "Cannon Lake U Premium", enable_flash_pch300},
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{0x8086, 0x0284, B_S, DEP, "Intel", "Comet Lake U Premium", enable_flash_pch400},
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{0x8086, 0x0285, B_S, DEP, "Intel", "Comet Lake U Base", enable_flash_pch400},
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{0x8086, 0xa082, B_S, DEP, "Intel", "Tiger Lake U Premium", enable_flash_pch500},
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{0x8086, 0xa141, B_S, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100},
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{0x8086, 0xa142, B_S, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100},
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{0x8086, 0xa143, B_S, DEP, "Intel", "H110", enable_flash_pch100},
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@ -45,6 +45,7 @@ ssize_t ich_number_of_regions(const enum ich_chipset cs, const struct ich_desc_c
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case CHIPSET_C620_SERIES_LEWISBURG:
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case CHIPSET_300_SERIES_CANNON_POINT:
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case CHIPSET_400_SERIES_COMET_POINT:
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case CHIPSET_500_SERIES_TIGER_POINT:
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return 16;
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case CHIPSET_100_SERIES_SUNRISE_POINT:
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return 10;
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@ -108,7 +109,7 @@ void prettyprint_ich_chipset(enum ich_chipset cs)
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"8 series Lynx Point", "Baytrail", "8 series Lynx Point LP", "8 series Wellsburg",
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"9 series Wildcat Point", "9 series Wildcat Point LP", "100 series Sunrise Point",
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"C620 series Lewisburg", "300 series Cannon Point", "400 series Comet Point",
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"Apollo Lake", "Gemini Lake",
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"500 series Tiger Point", "Apollo Lake", "Gemini Lake",
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};
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if (cs < CHIPSET_ICH8 || cs - CHIPSET_ICH8 + 1 >= ARRAY_SIZE(chipset_names))
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cs = 0;
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@ -202,6 +203,7 @@ static const char *pprint_density(enum ich_chipset cs, const struct ich_descript
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case CHIPSET_C620_SERIES_LEWISBURG:
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case CHIPSET_300_SERIES_CANNON_POINT:
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case CHIPSET_400_SERIES_COMET_POINT:
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE: {
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uint8_t size_enc;
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@ -222,7 +224,7 @@ static const char *pprint_density(enum ich_chipset cs, const struct ich_descript
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static const char *pprint_freq(enum ich_chipset cs, uint8_t value)
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{
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static const char *const freq_str[3][8] = { {
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static const char *const freq_str[4][8] = { {
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"20 MHz",
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"33 MHz",
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"reserved",
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@ -249,7 +251,16 @@ static const char *pprint_freq(enum ich_chipset cs, uint8_t value)
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"reserved",
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"14 MHz / 17 MHz",
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"reserved"
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} };
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}, {
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"100 MHz",
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"50 MHz",
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"reserved",
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"33 MHz",
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"25 MHz",
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"reserved",
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"14 MHz",
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"reserved"
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}};
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switch (cs) {
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case CHIPSET_ICH8:
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@ -276,12 +287,41 @@ static const char *pprint_freq(enum ich_chipset cs, uint8_t value)
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE:
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return freq_str[2][value];
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case CHIPSET_500_SERIES_TIGER_POINT:
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return freq_str[3][value];
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case CHIPSET_ICH_UNKNOWN:
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default:
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return "unknown";
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}
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}
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static void pprint_read_freq(enum ich_chipset cs, uint8_t value)
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{
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static const char *const freq_str[1][8] = { {
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"20 MHz",
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"24 MHz",
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"30 MHz",
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"48 MHz",
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"60 MHz",
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"reserved",
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"reserved",
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"reserved"
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}};
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switch (cs) {
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case CHIPSET_300_SERIES_CANNON_POINT:
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case CHIPSET_400_SERIES_COMET_POINT:
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msg_pdbg2("eSPI/EC Bus Clock Frequency: %s\n", freq_str[0][value]);
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return;
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case CHIPSET_500_SERIES_TIGER_POINT:
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msg_pdbg2("Read Clock Frequency: %s\n", "reserved");
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return;
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default:
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msg_pdbg2("Read Clock Frequency: %s\n", pprint_freq(cs, value));
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return;
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}
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}
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void prettyprint_ich_descriptor_component(enum ich_chipset cs, const struct ich_descriptors *desc)
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{
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bool has_flill1;
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@ -291,6 +331,7 @@ void prettyprint_ich_descriptor_component(enum ich_chipset cs, const struct ich_
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case CHIPSET_C620_SERIES_LEWISBURG:
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case CHIPSET_300_SERIES_CANNON_POINT:
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case CHIPSET_400_SERIES_COMET_POINT:
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE:
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has_flill1 = true;
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@ -313,7 +354,9 @@ void prettyprint_ich_descriptor_component(enum ich_chipset cs, const struct ich_
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msg_pdbg2("Component 2 density: %s\n", pprint_density(cs, desc, 1));
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else
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msg_pdbg2("Component 2 is not used.\n");
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msg_pdbg2("Read Clock Frequency: %s\n", pprint_freq(cs, desc->component.modes.freq_read));
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pprint_read_freq(cs, desc->component.modes.freq_read);
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msg_pdbg2("Read ID and Status Clock Freq.: %s\n", pprint_freq(cs, desc->component.modes.freq_read_id));
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msg_pdbg2("Write and Erase Clock Freq.: %s\n", pprint_freq(cs, desc->component.modes.freq_write));
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msg_pdbg2("Fast Read is %ssupported.\n", desc->component.modes.fastread ? "" : "not ");
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@ -411,7 +454,8 @@ void prettyprint_ich_descriptor_master(const enum ich_chipset cs, const struct i
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msg_pdbg2("--- Details ---\n");
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if (cs == CHIPSET_100_SERIES_SUNRISE_POINT ||
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cs == CHIPSET_300_SERIES_CANNON_POINT ||
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cs == CHIPSET_400_SERIES_COMET_POINT) {
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cs == CHIPSET_400_SERIES_COMET_POINT ||
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cs == CHIPSET_500_SERIES_TIGER_POINT) {
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const char *const master_names[] = {
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"BIOS", "ME", "GbE", "unknown", "EC",
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};
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@ -970,8 +1014,10 @@ static enum ich_chipset guess_ich_chipset_from_content(const struct ich_desc_con
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} else {
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if (content->ICCRIBA == 0x34)
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return CHIPSET_300_SERIES_CANNON_POINT;
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msg_pwarn("Unknown flash descriptor, assuming 300 series compatibility.\n");
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return CHIPSET_300_SERIES_CANNON_POINT;
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if (content->CSSL == 0x11)
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return CHIPSET_500_SERIES_TIGER_POINT;
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msg_pwarn("Unknown flash descriptor, assuming 500 series compatibility.\n");
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return CHIPSET_500_SERIES_TIGER_POINT;
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}
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}
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@ -990,6 +1036,7 @@ static enum ich_chipset guess_ich_chipset(const struct ich_desc_content *const c
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switch (guess) {
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case CHIPSET_300_SERIES_CANNON_POINT:
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case CHIPSET_400_SERIES_COMET_POINT:
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_GEMINI_LAKE:
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/* `freq_read` was repurposed, so can't check on it any more. */
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break;
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@ -1144,6 +1191,7 @@ int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors
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case CHIPSET_C620_SERIES_LEWISBURG:
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case CHIPSET_300_SERIES_CANNON_POINT:
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case CHIPSET_400_SERIES_COMET_POINT:
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE:
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if (idx == 0) {
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@ -1181,6 +1229,7 @@ static uint32_t read_descriptor_reg(enum ich_chipset cs, uint8_t section, uint16
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case CHIPSET_C620_SERIES_LEWISBURG:
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case CHIPSET_300_SERIES_CANNON_POINT:
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case CHIPSET_400_SERIES_COMET_POINT:
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE:
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mmio_le_writel(control, spibar + PCH100_REG_FDOC);
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@ -95,6 +95,13 @@ struct ich_desc_content {
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ICCRIBA :8, /* ICC Reg. Init Base Addr. (new since Sandy Bridge) */
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RIL :8; /* Register Init Length (new since Hawell) */
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};
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struct { /* new since Tiger Point */
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uint32_t :2,
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CSSO :10, /* CPU Soft Strap Offset from PMC Base */
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:4,
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CSSL :8, /* CPU Soft Strap Length */
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:8;
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};
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};
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};
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11
ichspi.c
11
ichspi.c
@ -426,6 +426,7 @@ static void prettyprint_ich9_reg_hsfs(uint16_t reg_val, enum ich_chipset ich_gen
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case CHIPSET_C620_SERIES_LEWISBURG:
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case CHIPSET_300_SERIES_CANNON_POINT:
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case CHIPSET_400_SERIES_COMET_POINT:
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case CHIPSET_500_SERIES_TIGER_POINT:
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break;
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default:
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pprint_reg(HSFS, BERASE, reg_val, ", ");
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@ -437,6 +438,7 @@ static void prettyprint_ich9_reg_hsfs(uint16_t reg_val, enum ich_chipset ich_gen
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case CHIPSET_C620_SERIES_LEWISBURG:
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case CHIPSET_300_SERIES_CANNON_POINT:
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case CHIPSET_400_SERIES_COMET_POINT:
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case CHIPSET_500_SERIES_TIGER_POINT:
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pprint_reg(HSFS, PRR34_LOCKDN, reg_val, ", ");
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pprint_reg(HSFS, WRSDIS, reg_val, ", ");
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break;
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@ -457,6 +459,7 @@ static void prettyprint_ich9_reg_hsfc(uint16_t reg_val, enum ich_chipset ich_gen
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case CHIPSET_C620_SERIES_LEWISBURG:
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case CHIPSET_300_SERIES_CANNON_POINT:
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case CHIPSET_400_SERIES_COMET_POINT:
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case CHIPSET_500_SERIES_TIGER_POINT:
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_pprint_reg(HSFC, PCH100_HSFC_FCYCLE, PCH100_HSFC_FCYCLE_OFF, reg_val, ", ");
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pprint_reg(HSFC, WET, reg_val, ", ");
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break;
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@ -1735,6 +1738,7 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
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case CHIPSET_C620_SERIES_LEWISBURG:
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case CHIPSET_300_SERIES_CANNON_POINT:
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case CHIPSET_400_SERIES_COMET_POINT:
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE:
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num_pr = 6; /* Includes GPR0 */
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@ -1768,6 +1772,7 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
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break;
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case CHIPSET_300_SERIES_CANNON_POINT:
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case CHIPSET_400_SERIES_COMET_POINT:
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE:
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num_freg = 16;
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@ -1865,6 +1870,7 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
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case CHIPSET_C620_SERIES_LEWISBURG:
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case CHIPSET_300_SERIES_CANNON_POINT:
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case CHIPSET_400_SERIES_COMET_POINT:
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE:
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tmp = mmio_readl(spibar + PCH100_REG_DLOCK);
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@ -1941,6 +1947,7 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
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case CHIPSET_C620_SERIES_LEWISBURG:
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case CHIPSET_300_SERIES_CANNON_POINT:
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case CHIPSET_400_SERIES_COMET_POINT:
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE:
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case CHIPSET_BAYTRAIL:
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@ -1975,6 +1982,7 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
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case CHIPSET_C620_SERIES_LEWISBURG:
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case CHIPSET_300_SERIES_CANNON_POINT:
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case CHIPSET_400_SERIES_COMET_POINT:
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case CHIPSET_500_SERIES_TIGER_POINT:
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE:
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break;
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@ -2008,7 +2016,8 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
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if (ich_spi_mode == ich_auto &&
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(ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT ||
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ich_gen == CHIPSET_300_SERIES_CANNON_POINT ||
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ich_gen == CHIPSET_400_SERIES_COMET_POINT)) {
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ich_gen == CHIPSET_400_SERIES_COMET_POINT ||
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ich_gen == CHIPSET_500_SERIES_TIGER_POINT)) {
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msg_pdbg("Enabling hardware sequencing by default for 100+ series PCH.\n");
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ich_spi_mode = ich_hwseq;
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}
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@ -359,6 +359,7 @@ enum ich_chipset {
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CHIPSET_C620_SERIES_LEWISBURG,
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CHIPSET_300_SERIES_CANNON_POINT,
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CHIPSET_400_SERIES_COMET_POINT,
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CHIPSET_500_SERIES_TIGER_POINT,
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CHIPSET_APOLLO_LAKE,
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CHIPSET_GEMINI_LAKE,
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};
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@ -136,6 +136,7 @@ static void usage(char *argv[], const char *error)
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"\t- \"100\" or \"sunrise\" for Intel's 100 series chipsets.\n"
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"\t- \"300\" or \"cannon\" for Intel's 300 series chipsets.\n"
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"\t- \"400\" or \"comet\" for Intel's 400 series chipsets.\n"
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"\t- \"500\" or \"tiger\" for Intel's 500 series chipsets.\n"
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"If '-d' is specified some regions such as the BIOS image as seen by the CPU or\n"
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"the GbE blob that is required to initialize the GbE are also dumped to files.\n",
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argv[0], argv[0]);
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@ -230,6 +231,9 @@ int main(int argc, char *argv[])
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else if ((strcmp(csn, "400") == 0) ||
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||||
(strcmp(csn, "comet") == 0))
|
||||
cs = CHIPSET_400_SERIES_COMET_POINT;
|
||||
else if ((strcmp(csn, "500") == 0) ||
|
||||
(strcmp(csn, "tiger") == 0))
|
||||
cs = CHIPSET_500_SERIES_TIGER_POINT;
|
||||
else if (strcmp(csn, "apollo") == 0)
|
||||
cs = CHIPSET_APOLLO_LAKE;
|
||||
else if (strcmp(csn, "gemini") == 0)
|
||||
|
||||
Reference in New Issue
Block a user