mirror of
https://review.coreboot.org/flashrom.git
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flashchips.c: add writeprotect support for more chips
Chips I had available for testing were tested with all writeprotect
commands and an FT232H adapter. Chips I wasn't able to test were just
checked against the datasheets.
Chips used for testing (including chips added in previous patches) are
listed in the table below:
Flashrom Chip name | Chip(s) tested
---------------------------------+----------------------------
AT25SL128A |
EN25QH128 |
GD25LQ128C/GD25LQ128D/GD25LQ128E | GD25LQ128DSIG
GD25LQ64(B) | GD25LQ64CWIG
GD25Q127C/GD25Q128C | GD25Q127CSIG, GD25Q128ESIG
GD25Q256D | GD25Q256DYIG
GD25Q64(B) | GD25Q64CSIG
W25Q128.JW.DTR |
W25Q128.V..M |
W25Q128.W |
W25Q256JV_M |
W25Q256.V |
W25Q64.W |
XM25QH128C |
XM25QH256C |
BUG=b:182223106
BRANCH=none
TEST=flashrom --wp-{enable,disable,range,list,status}
Change-Id: I7f3d4c4148056098a845b5c64308b0333ebda395
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62214
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nikolai Artemiev
Edward O'Callaghan
parent
632bdcb9e2
commit
a850fd0aa8
152
flashchips.c
152
flashchips.c
@ -2414,7 +2414,7 @@ const struct flashchip flashchips[] = {
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.total_size = 16384,
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.page_size = 256,
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/* supports SFDP */
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI,
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_WRSR2,
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.tested = TEST_OK_PREW,
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.probe = probe_spi_rdid,
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.probe_timing = TIMING_ZERO,
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@ -2442,6 +2442,16 @@ const struct flashchip flashchips[] = {
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.write = spi_chip_write_256,
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.read = spi_chip_read,
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.voltage = {1700, 2000},
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.reg_bits =
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{
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.srp = {STATUS1, 7, RW},
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.srl = {STATUS2, 0, RW},
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.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
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.tb = {STATUS1, 5, RW},
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.sec = {STATUS1, 6, RW},
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.cmp = {STATUS2, 6, RW},
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},
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.decode_range = decode_range_spi25,
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},
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{
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@ -5167,6 +5177,13 @@ const struct flashchip flashchips[] = {
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.write = spi_chip_write_256,
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.read = spi_chip_read,
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.voltage = {2700, 3600},
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.reg_bits =
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{
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.srp = {STATUS1, 7, RW},
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.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
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.tb = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like TB */
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},
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.decode_range = decode_range_spi25,
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},
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{
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@ -6483,7 +6500,7 @@ const struct flashchip flashchips[] = {
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.total_size = 8192,
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.page_size = 256,
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/* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR_EXT,
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.tested = TEST_OK_PREW,
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.probe = probe_spi_rdid,
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.probe_timing = TIMING_ZERO,
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@ -6511,6 +6528,16 @@ const struct flashchip flashchips[] = {
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.write = spi_chip_write_256,
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.read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
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.voltage = {1695, 1950},
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.reg_bits =
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{
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.srp = {STATUS1, 7, RW},
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.srl = {STATUS2, 0, RW},
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.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
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.tb = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like TB */
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.sec = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like SEC */
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.cmp = {STATUS2, 6, RW},
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},
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.decode_range = decode_range_spi25,
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},
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{
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@ -6600,7 +6627,7 @@ const struct flashchip flashchips[] = {
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.page_size = 256,
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/* OTP: 1536B total; read 0x48; write 0x42, erase 0x44 */
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/* QPI: enable 0x38, disable 0xFF */
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI,
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_WRSR2,
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.tested = TEST_OK_PREW,
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.probe = probe_spi_rdid,
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.probe_timing = TIMING_ZERO,
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@ -6629,6 +6656,16 @@ const struct flashchip flashchips[] = {
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.write = spi_chip_write_256,
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.read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
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.voltage = {2700, 3600},
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.reg_bits =
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{
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.srp = {STATUS1, 7, RW},
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.srl = {STATUS2, 0, RW},
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.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
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.tb = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like TB */
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.sec = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like SEC */
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.cmp = {STATUS2, 6, RW},
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},
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.decode_range = decode_range_spi25,
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},
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{
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@ -6895,7 +6932,7 @@ const struct flashchip flashchips[] = {
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.total_size = 8192,
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.page_size = 256,
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/* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR2,
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.tested = TEST_OK_PREW,
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.probe = probe_spi_rdid,
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.probe_timing = TIMING_ZERO,
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@ -6923,6 +6960,16 @@ const struct flashchip flashchips[] = {
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.write = spi_chip_write_256,
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.read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
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.voltage = {2700, 3600},
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.reg_bits =
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{
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.srp = {STATUS1, 7, RW},
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.srl = {STATUS2, 0, RW},
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.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
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.tb = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like TB */
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.sec = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like SEC */
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.cmp = {STATUS2, 6, RW},
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},
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.decode_range = decode_range_spi25,
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},
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{
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@ -17172,7 +17219,7 @@ const struct flashchip flashchips[] = {
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.model_id = WINBOND_NEX_W25Q128_V_M,
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.total_size = 16384,
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.page_size = 256,
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI,
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_WRSR2,
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.tested = TEST_OK_PREW,
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.probe = probe_spi_rdid,
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.probe_timing = TIMING_ZERO,
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@ -17200,6 +17247,16 @@ const struct flashchip flashchips[] = {
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.write = spi_chip_write_256,
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.read = spi_chip_read,
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.voltage = {2700, 3600},
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.reg_bits =
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{
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.srp = {STATUS1, 7, RW},
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.srl = {STATUS2, 0, RW},
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.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
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.tb = {STATUS1, 5, RW},
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.sec = {STATUS1, 6, RW},
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.cmp = {STATUS2, 6, RW},
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},
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.decode_range = decode_range_spi25,
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},
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{
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@ -17212,7 +17269,7 @@ const struct flashchip flashchips[] = {
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.page_size = 256,
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/* supports SFDP */
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/* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI,
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_WRSR2,
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.tested = TEST_OK_PREW,
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.probe = probe_spi_rdid,
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.probe_timing = TIMING_ZERO,
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@ -17240,6 +17297,16 @@ const struct flashchip flashchips[] = {
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.write = spi_chip_write_256,
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.read = spi_chip_read,
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.voltage = {1650, 1950},
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.reg_bits =
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{
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.srp = {STATUS1, 7, RW},
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.srl = {STATUS2, 0, RW},
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.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
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.tb = {STATUS1, 5, RW},
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.sec = {STATUS1, 6, RW},
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.cmp = {STATUS2, 6, RW},
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},
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.decode_range = decode_range_spi25,
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},
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{
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@ -17250,7 +17317,7 @@ const struct flashchip flashchips[] = {
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.model_id = WINBOND_NEX_W25Q128_DTR,
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.total_size = 16384,
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.page_size = 256,
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI,
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_WRSR2,
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.tested = TEST_OK_PREW,
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.probe = probe_spi_rdid,
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.probe_timing = TIMING_ZERO,
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@ -17278,6 +17345,16 @@ const struct flashchip flashchips[] = {
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.write = spi_chip_write_256,
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.read = spi_chip_read,
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.voltage = {1650, 1950},
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.reg_bits =
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{
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.srp = {STATUS1, 7, RW},
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.srl = {STATUS2, 0, RW},
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.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
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.tb = {STATUS1, 5, RW},
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.sec = {STATUS1, 6, RW},
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.cmp = {STATUS2, 6, RW},
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},
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.decode_range = decode_range_spi25,
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},
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{
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@ -17410,8 +17487,9 @@ const struct flashchip flashchips[] = {
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/* supports SFDP */
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/* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */
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/* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN
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| FEATURE_4BA_EXT_ADDR | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ,
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN |
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FEATURE_4BA_EXT_ADDR | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ |
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FEATURE_WRSR2,
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.tested = TEST_OK_PREW,
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.probe = probe_spi_rdid,
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.probe_timing = TIMING_ZERO,
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@ -17439,6 +17517,14 @@ const struct flashchip flashchips[] = {
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.write = spi_chip_write_256,
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.read = spi_chip_read,
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.voltage = {2700, 3600},
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.reg_bits =
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{
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.srp = {STATUS1, 7, RW},
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.srl = {STATUS2, 0, RW},
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.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
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.tb = {STATUS1, 6, RW},
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},
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.decode_range = decode_range_spi25,
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},
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{
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@ -17452,7 +17538,7 @@ const struct flashchip flashchips[] = {
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/* supports SFDP */
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/* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */
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/* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA,
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA | FEATURE_WRSR2,
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.tested = TEST_OK_PREW,
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.probe = probe_spi_rdid,
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.probe_timing = TIMING_ZERO,
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@ -17486,6 +17572,15 @@ const struct flashchip flashchips[] = {
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.write = spi_chip_write_256,
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.read = spi_chip_read,
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.voltage = {2700, 3600},
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.reg_bits =
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{
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.srp = {STATUS1, 7, RW},
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.srl = {STATUS2, 0, RW},
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.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
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.tb = {STATUS1, 6, RW},
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.cmp = {STATUS2, 6, RW},
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},
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.decode_range = decode_range_spi25,
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},
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{
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@ -17946,7 +18041,7 @@ const struct flashchip flashchips[] = {
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.page_size = 256,
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/* OTP: 256B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */
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/* QPI enable 0x38, disable 0xFF */
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI,
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_WRSR2,
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.tested = TEST_OK_PREW,
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.probe = probe_spi_rdid,
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.probe_timing = TIMING_ZERO,
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@ -17974,6 +18069,16 @@ const struct flashchip flashchips[] = {
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.write = spi_chip_write_256,
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.read = spi_chip_read,
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.voltage = {1700, 1950}, /* Fast read (0x0B) and multi I/O supported */
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.reg_bits =
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{
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.srp = {STATUS1, 7, RW},
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.srl = {STATUS2, 0, RW},
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.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
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.tb = {STATUS1, 5, RW},
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.sec = {STATUS1, 6, RW},
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.cmp = {STATUS2, 6, RW},
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},
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.decode_range = decode_range_spi25,
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},
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{
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@ -19308,7 +19413,7 @@ const struct flashchip flashchips[] = {
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.model_id = XMC_XM25QH128C,
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.total_size = 16384,
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.page_size = 256,
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI,
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_WRSR2,
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.tested = TEST_UNTESTED,
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.probe = probe_spi_rdid,
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.probe_timing = TIMING_ZERO,
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@ -19336,6 +19441,16 @@ const struct flashchip flashchips[] = {
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.write = spi_chip_write_256,
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.read = spi_chip_read,
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.voltage = {2700, 3600},
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.reg_bits =
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{
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.srp = {STATUS1, 7, RW},
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.srl = {STATUS2, 0, RW},
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.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
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.tb = {STATUS1, 5, RW},
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.sec = {STATUS1, 6, RW},
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.cmp = {STATUS2, 6, RW},
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},
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.decode_range = decode_range_spi25,
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},
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{
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@ -19389,8 +19504,9 @@ const struct flashchip flashchips[] = {
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/* supports SFDP */
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/* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */
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/* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN
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| FEATURE_4BA_EXT_ADDR | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ,
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN |
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FEATURE_4BA_EXT_ADDR | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ |
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FEATURE_WRSR2,
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.tested = TEST_UNTESTED,
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.probe = probe_spi_rdid,
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.probe_timing = TIMING_ZERO,
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@ -19418,6 +19534,14 @@ const struct flashchip flashchips[] = {
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.write = spi_chip_write_256,
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.read = spi_chip_read,
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.voltage = {2700, 3600},
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.reg_bits =
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{
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.srp = {STATUS1, 7, RW},
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.srl = {STATUS2, 0, RW},
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.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
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.tb = {STATUS1, 6, RW},
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},
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.decode_range = decode_range_spi25,
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},
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{
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