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https://review.coreboot.org/flashrom.git
synced 2025-04-28 23:43:42 +02:00
ichspi: Remove unneeded line breaks, add useful line breaks and tabs
BUG=b:204488958 TEST=Check that the following scenarios still behave properly: 1) probe-read-verify-erase section-write-reboot on Intel octopus board with GD25LQ128C/GD25LQ128D/GD25LQ128E 2) flashrom binary built before and after this patch with command `make clean && make CONFIG_EVERYTHING=yes VERSION=none` is the same Change-Id: I7ca2902b7caaa95418b828b068c661afafdcd171 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/60272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Anastasia Klimchuk
Nico Huber
parent
97a1683c85
commit
ac68a9e2a8
94
ichspi.c
94
ichspi.c
@ -926,8 +926,7 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset,
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programmer_delay(10);
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}
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if (!timeout) {
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msg_perr("timeout, ICH7_REG_SPIS=0x%04x\n",
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REGREAD16(ICH7_REG_SPIS));
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msg_perr("timeout, ICH7_REG_SPIS=0x%04x\n", REGREAD16(ICH7_REG_SPIS));
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return 1;
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}
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@ -995,8 +994,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset,
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if (datalength != 0) {
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uint32_t datatemp;
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temp32 |= SSFC_DS;
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datatemp = ((((uint32_t)datalength - 1) << SSFC_DBC_OFF) &
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SSFC_DBC);
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datatemp = ((((uint32_t)datalength - 1) << SSFC_DBC_OFF) & SSFC_DBC);
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temp32 |= datatemp;
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}
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@ -1048,8 +1046,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset,
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programmer_delay(10);
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}
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if (!timeout) {
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msg_perr("timeout, REG_SSFS=0x%08x\n",
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REGREAD32(swseq_data.reg_ssfsc));
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msg_perr("timeout, REG_SSFS=0x%08x\n", REGREAD32(swseq_data.reg_ssfsc));
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return 1;
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}
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@ -1123,8 +1120,7 @@ static int ich_spi_send_command(const struct flashctx *flash, unsigned int write
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msg_pdbg("OPCODE 0x%02x has unsupported length, will not execute.\n", cmd);
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return SPI_INVALID_LENGTH;
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} else if (opcode_index == -1) {
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msg_pdbg("Invalid OPCODE 0x%02x, will not execute.\n",
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cmd);
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msg_pdbg("Invalid OPCODE 0x%02x, will not execute.\n", cmd);
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return SPI_INVALID_OPCODE;
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}
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}
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@ -1141,30 +1137,26 @@ static int ich_spi_send_command(const struct flashctx *flash, unsigned int write
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if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS) &&
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(writecnt != 4)) {
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msg_perr("%s: Internal command size error for opcode "
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"0x%02x, got writecnt=%i, want =4\n", __func__, cmd,
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writecnt);
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"0x%02x, got writecnt=%i, want =4\n", __func__, cmd, writecnt);
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return SPI_INVALID_LENGTH;
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}
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if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_NO_ADDRESS) &&
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(writecnt != 1)) {
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msg_perr("%s: Internal command size error for opcode "
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"0x%02x, got writecnt=%i, want =1\n", __func__, cmd,
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writecnt);
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"0x%02x, got writecnt=%i, want =1\n", __func__, cmd, writecnt);
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return SPI_INVALID_LENGTH;
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}
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if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) &&
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(writecnt < 4)) {
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msg_perr("%s: Internal command size error for opcode "
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"0x%02x, got writecnt=%i, want >=4\n", __func__, cmd,
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writecnt);
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"0x%02x, got writecnt=%i, want >=4\n", __func__, cmd, writecnt);
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return SPI_INVALID_LENGTH;
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}
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if (((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
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(opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) &&
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(readcnt)) {
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msg_perr("%s: Internal command size error for opcode "
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"0x%02x, got readcnt=%i, want =0\n", __func__, cmd,
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readcnt);
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"0x%02x, got readcnt=%i, want =0\n", __func__, cmd, readcnt);
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return SPI_INVALID_LENGTH;
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}
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@ -1356,8 +1348,7 @@ static int ich_hwseq_probe(struct flashctx *flash)
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eraser->eraseblocks[0].size = erase_size_low;
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eraser->eraseblocks[0].count = size_low / erase_size_low;
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msg_cdbg("The first partition ranges from 0x%06x to 0x%06x.\n",
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0, size_low-1);
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msg_cdbg("The first partition ranges from 0x%06x to 0x%06x.\n", 0, size_low-1);
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msg_cdbg("In that range are %d erase blocks with %d B each.\n",
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size_low / erase_size_low, erase_size_low);
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@ -1398,8 +1389,7 @@ static int ich_hwseq_block_erase(struct flashctx *flash, unsigned int addr,
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if (addr + len > flash->chip->total_size * 1024) {
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msg_perr("Request to erase some inaccessible memory address(es)"
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" (addr=0x%x, len=%d). "
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"Not erasing anything.\n", addr, len);
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" (addr=0x%x, len=%d). Not erasing anything.\n", addr, len);
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return -1;
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}
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@ -1717,29 +1707,22 @@ static int init_ich7_spi(void *spibar, enum ich_chipset ich_gen)
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{
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unsigned int i;
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msg_pdbg("0x00: 0x%04x (SPIS)\n",
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mmio_readw(spibar + 0));
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msg_pdbg("0x02: 0x%04x (SPIC)\n",
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mmio_readw(spibar + 2));
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msg_pdbg("0x04: 0x%08x (SPIA)\n",
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mmio_readl(spibar + 4));
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msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(spibar + 0));
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msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(spibar + 2));
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msg_pdbg("0x04: 0x%08x (SPIA)\n", mmio_readl(spibar + 4));
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ichspi_bbar = mmio_readl(spibar + 0x50);
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msg_pdbg("0x50: 0x%08x (BBAR)\n",
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ichspi_bbar);
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msg_pdbg("0x54: 0x%04x (PREOP)\n",
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mmio_readw(spibar + 0x54));
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msg_pdbg("0x56: 0x%04x (OPTYPE)\n",
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mmio_readw(spibar + 0x56));
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msg_pdbg("0x58: 0x%08x (OPMENU)\n",
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mmio_readl(spibar + 0x58));
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msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n",
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mmio_readl(spibar + 0x5c));
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msg_pdbg("0x50: 0x%08x (BBAR)\n", ichspi_bbar);
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msg_pdbg("0x54: 0x%04x (PREOP)\n", mmio_readw(spibar + 0x54));
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msg_pdbg("0x56: 0x%04x (OPTYPE)\n", mmio_readw(spibar + 0x56));
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msg_pdbg("0x58: 0x%08x (OPMENU)\n", mmio_readl(spibar + 0x58));
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msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", mmio_readl(spibar + 0x5c));
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for (i = 0; i < 3; i++) {
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int offs;
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offs = 0x60 + (i * 4);
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msg_pdbg("0x%02x: 0x%08x (PBR%u)\n", offs,
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mmio_readl(spibar + offs), i);
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msg_pdbg("0x%02x: 0x%08x (PBR%u)\n", offs, mmio_readl(spibar + offs), i);
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}
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if (mmio_readw(spibar) & (1 << 15)) {
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msg_pwarn("WARNING: SPI Configuration Lockdown activated.\n");
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@ -1932,8 +1915,7 @@ static int init_ich_default(void *spibar, enum ich_chipset ich_gen)
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case LOCKED:
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msg_pwarn("At least some flash regions are read protected. You have to use a flash\n"
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"layout and include only accessible regions. For write operations, you'll\n"
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"additionally need the --noverify-all switch. See manpage for more details.\n"
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);
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"additionally need the --noverify-all switch. See manpage for more details.\n");
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break;
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}
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@ -2016,8 +1998,7 @@ static int init_ich_default(void *spibar, enum ich_chipset ich_gen)
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* access the second flash device.
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*/
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if (ich_spi_mode == ich_auto && desc.content.NC != 0) {
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msg_pinfo("Enabling hardware sequencing due to "
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"multiple flash chips detected.\n");
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msg_pinfo("Enabling hardware sequencing due to multiple flash chips detected.\n");
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ich_spi_mode = ich_hwseq;
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}
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}
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@ -2048,8 +2029,7 @@ static int init_ich_default(void *spibar, enum ich_chipset ich_gen)
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if (ich_spi_mode == ich_hwseq) {
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if (!desc_valid) {
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msg_perr("Hardware sequencing was requested "
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"but the flash descriptor is not "
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"valid. Aborting.\n");
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"but the flash descriptor is not valid. Aborting.\n");
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return ERROR_FATAL;
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}
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@ -2115,31 +2095,29 @@ int via_init_spi(uint32_t mmio_base)
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ich_generation = CHIPSET_ICH7;
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register_spi_master(&spi_master_via, NULL);
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msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0));
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msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2));
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msg_pdbg("0x04: 0x%08x (SPIA)\n", mmio_readl(ich_spibar + 4));
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msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0));
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msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2));
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msg_pdbg("0x04: 0x%08x (SPIA)\n", mmio_readl(ich_spibar + 4));
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for (i = 0; i < 2; i++) {
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int offs;
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offs = 8 + (i * 8);
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msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs,
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mmio_readl(ich_spibar + offs), i);
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msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs, mmio_readl(ich_spibar + offs), i);
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msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
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mmio_readl(ich_spibar + offs + 4), i);
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}
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ichspi_bbar = mmio_readl(ich_spibar + 0x50);
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msg_pdbg("0x50: 0x%08x (BBAR)\n", ichspi_bbar);
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msg_pdbg("0x54: 0x%04x (PREOP)\n", mmio_readw(ich_spibar + 0x54));
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msg_pdbg("0x56: 0x%04x (OPTYPE)\n", mmio_readw(ich_spibar + 0x56));
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msg_pdbg("0x58: 0x%08x (OPMENU)\n", mmio_readl(ich_spibar + 0x58));
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msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", mmio_readl(ich_spibar + 0x5c));
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msg_pdbg("0x50: 0x%08x (BBAR)\n", ichspi_bbar);
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msg_pdbg("0x54: 0x%04x (PREOP)\n", mmio_readw(ich_spibar + 0x54));
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msg_pdbg("0x56: 0x%04x (OPTYPE)\n", mmio_readw(ich_spibar + 0x56));
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msg_pdbg("0x58: 0x%08x (OPMENU)\n", mmio_readl(ich_spibar + 0x58));
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msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", mmio_readl(ich_spibar + 0x5c));
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for (i = 0; i < 3; i++) {
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int offs;
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offs = 0x60 + (i * 4);
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msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs,
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mmio_readl(ich_spibar + offs), i);
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msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs, mmio_readl(ich_spibar + offs), i);
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}
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msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n",
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mmio_readw(ich_spibar + 0x6c));
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msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n", mmio_readw(ich_spibar + 0x6c));
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if (mmio_readw(ich_spibar) & (1 << 15)) {
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msg_pwarn("Warning: SPI Configuration Lockdown activated.\n");
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ichspi_lock = 1;
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