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Intel 28F004/28F400 support
Remove blockwise write for i82802ab chips. It will be reintroduced in post-0.9.2 in a generic way. This is needed to fix FWH-like chips with non-uniform sectors. These are: Intel 28F001 Sharp LHF00L04 ST M50FW002 ST M50LPW116 Corresponding to flashrom svn r991. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
This commit is contained in:
Michael Karcher
parent
253101e69e
commit
ad0010a67a
52
82802ab.c
52
82802ab.c
@ -48,6 +48,7 @@ int probe_82802ab(struct flashchip *flash)
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chipaddr bios = flash->virtual_memory;
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uint8_t id1, id2;
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uint8_t flashcontent1, flashcontent2;
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int shifted = (flash->feature_bits & FEATURE_ADDR_SHIFTED) != 0;
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/* Reset to get a clean state */
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chip_writeb(0xFF, bios);
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@ -57,8 +58,8 @@ int probe_82802ab(struct flashchip *flash)
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chip_writeb(0x90, bios);
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programmer_delay(10);
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id1 = chip_readb(bios);
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id2 = chip_readb(bios + 0x01);
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id1 = chip_readb(bios + (0x00 << shifted));
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id2 = chip_readb(bios + (0x01 << shifted));
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/* Leave ID mode */
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chip_writeb(0xFF, bios);
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@ -71,8 +72,8 @@ int probe_82802ab(struct flashchip *flash)
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msg_cdbg(", id1 parity violation");
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/* Read the product ID location again. We should now see normal flash contents. */
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flashcontent1 = chip_readb(bios);
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flashcontent2 = chip_readb(bios + 0x01);
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flashcontent1 = chip_readb(bios + (0x00 << shifted));
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flashcontent2 = chip_readb(bios + (0x01 << shifted));
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if (id1 == flashcontent1)
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msg_cdbg(", id1 is normal flash content");
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@ -178,44 +179,25 @@ void write_page_82802ab(chipaddr bios, uint8_t *src,
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int write_82802ab(struct flashchip *flash, uint8_t *buf)
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{
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int i;
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int total_size = flash->total_size * 1024;
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int page_size = flash->page_size;
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chipaddr bios = flash->virtual_memory;
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uint8_t *tmpbuf = malloc(page_size);
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if (!tmpbuf) {
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msg_cerr("Could not allocate memory!\n");
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exit(1);
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if (erase_flash(flash)) {
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msg_cerr("ERASE FAILED!\n");
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return -1;
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}
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msg_cinfo("Programming page: \n");
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for (i = 0; i < total_size / page_size; i++) {
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msg_cinfo("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b");
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msg_cinfo("%04d at address: 0x%08x", i, i * page_size);
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/* Auto Skip Blocks, which already contain the desired data
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* Faster, because we only write, what has changed
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* More secure, because blocks, which are excluded
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* (with the exclude or layout feature)
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* or not erased and rewritten; their data is retained also in
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* sudden power off situations
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*/
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chip_readn(tmpbuf, bios + i * page_size, page_size);
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if (!memcmp((void *)(buf + i * page_size), tmpbuf, page_size)) {
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msg_cdbg("SKIPPED\n");
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continue;
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}
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msg_cinfo("Programming at: ");
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for (i = 0; i < flash->total_size; i++) {
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if ((i & 0x3) == 0)
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msg_cinfo("address: 0x%08lx", (unsigned long)i * 1024);
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/* erase block by block and write block by block; this is the most secure way */
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if (erase_block_82802ab(flash, i * page_size, page_size)) {
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msg_cerr("ERASE FAILED!\n");
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return -1;
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}
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write_page_82802ab(bios, buf + i * page_size,
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bios + i * page_size, page_size);
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write_page_82802ab(bios, buf + i * 1024, bios + i * 1024, 1024);
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if ((i & 0x3) == 0)
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msg_cinfo("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b");
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}
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msg_cinfo("DONE!\n");
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free(tmpbuf);
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return 0;
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}
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2
flash.h
2
flash.h
@ -166,7 +166,7 @@ enum chipbustype {
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#define FEATURE_ADDR_MASK (3 << 2)
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#define FEATURE_ADDR_2AA (1 << 2)
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#define FEATURE_ADDR_AAA (2 << 2)
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#define FEATURE_ADDR_SHIFTED 0
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#define FEATURE_ADDR_SHIFTED (1 << 5)
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struct flashchip {
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const char *vendor;
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110
flashchips.c
110
flashchips.c
@ -2383,6 +2383,116 @@ struct flashchip flashchips[] = {
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.read = read_memmapped,
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},
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{
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.vendor = "Intel",
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.name = "28F004BV/BE-B",
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.bustype = CHIP_BUSTYPE_PARALLEL,
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.manufacture_id = INTEL_ID,
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.model_id = P28F004BB,
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.total_size = 512,
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.page_size = 128 * 1024, /* maximal block size */
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.tested = TEST_UNTESTED,
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.probe = probe_82802ab,
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.probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */
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.block_erasers =
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{
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{
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.eraseblocks = {
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{16 * 1024, 1},
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{8 * 1024, 2},
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{96 * 1024, 1},
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{128 * 1024, 3},
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},
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.block_erase = erase_block_82802ab,
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},
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},
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.write = write_82802ab,
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.read = read_memmapped,
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},
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{
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.vendor = "Intel",
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.name = "28F004BV/BE-T",
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.bustype = CHIP_BUSTYPE_PARALLEL,
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.manufacture_id = INTEL_ID,
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.model_id = P28F004BT,
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.total_size = 512,
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.page_size = 128 * 1024, /* maximal block size */
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.tested = TEST_UNTESTED,
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.probe = probe_82802ab,
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.probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */
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.block_erasers =
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{
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{
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.eraseblocks = {
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{128 * 1024, 3},
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{96 * 1024, 1},
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{8 * 1024, 2},
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{16 * 1024, 1},
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},
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.block_erase = erase_block_82802ab,
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},
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},
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.write = write_82802ab,
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.read = read_memmapped,
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},
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{
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.vendor = "Intel",
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.name = "28F400BV/CV/CE-B",
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.bustype = CHIP_BUSTYPE_PARALLEL,
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.manufacture_id = INTEL_ID,
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.model_id = P28F400BB,
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.total_size = 512,
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.page_size = 128 * 1024, /* maximal block size */
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.feature_bits = FEATURE_ADDR_SHIFTED,
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.tested = TEST_UNTESTED,
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.probe = probe_82802ab,
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.probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */
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.block_erasers =
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{
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{
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.eraseblocks = {
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{16 * 1024, 1},
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{8 * 1024, 2},
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{96 * 1024, 1},
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{128 * 1024, 3},
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},
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.block_erase = erase_block_82802ab,
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},
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},
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.write = write_82802ab,
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.read = read_memmapped,
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},
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{
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.vendor = "Intel",
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.name = "28F400BV/CV/CE-T",
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.bustype = CHIP_BUSTYPE_PARALLEL,
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.manufacture_id = INTEL_ID,
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.model_id = P28F400BT,
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.total_size = 512,
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.page_size = 128 * 1024, /* maximal block size */
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.feature_bits = FEATURE_ADDR_SHIFTED,
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.tested = TEST_UNTESTED,
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.probe = probe_82802ab,
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.probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */
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.block_erasers =
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{
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{
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.eraseblocks = {
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{128 * 1024, 3},
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{96 * 1024, 1},
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{8 * 1024, 2},
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{16 * 1024, 1},
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},
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.block_erase = erase_block_82802ab,
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},
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},
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.write = write_82802ab,
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.read = read_memmapped,
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},
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{
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.vendor = "Intel",
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.name = "82802AB",
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@ -259,6 +259,10 @@
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#define E_28F016S5 0xAA
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#define P28F001BXT 0x94 /* 28F001BX-T */
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#define P28F001BXB 0x95 /* 28F001BX-B */
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#define P28F004BT 0x78 /* 28F004BV/BE-T */
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#define P28F004BB 0x79 /* 28F004BV/BE-B */
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#define P28F400BT 0x70 /* 28F400BV/CV/CE-T */
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#define P28F400BB 0x71 /* 28F400BV/CV/CE-B */
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#define SHARP_LH28F008SA 0xA2 /* Sharp chip, Intel Vendor ID */
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#define SHARP_LH28F008SC 0xA6 /* Sharp chip, Intel Vendor ID */
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