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mirror of https://review.coreboot.org/flashrom.git synced 2025-04-26 22:52:34 +02:00

flashchips: add support for MX77L25650F chip

Add initial support for Macronix MX77L25650F. Can read, write and erase
the chip.

Change-Id: Iaea5485f8b59b8538dc47beada2c308376ea027c
Signed-off-by: Artur Kowalski <artur.kowalski@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Signed-off-by: ServError <admin@serverror.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/68557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
This commit is contained in:
Artur Kowalski 2022-10-19 16:37:10 +02:00 committed by Anastasia Klimchuk
parent aac723f184
commit af8c203436
2 changed files with 41 additions and 0 deletions

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@ -10854,6 +10854,46 @@ const struct flashchip flashchips[] = {
.voltage = {2700, 3600},
},
{
.vendor = "Macronix",
.name = "MX77L25650F",
.bustype = BUS_SPI,
.manufacture_id = MACRONIX_ID,
.model_id = MACRONIX_MX77L25650F,
.total_size = 32768,
.page_size = 256,
/* OTP: 512B total; enter 0xB1, exit 0xC1 */
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA,
.tested = TEST_OK_PREW,
.probe = PROBE_SPI_RDID,
.probe_timing = TIMING_ZERO,
.block_erasers =
{
{
.eraseblocks = { {4 * 1024, 8192} },
.block_erase = SPI_BLOCK_ERASE_20,
}, {
.eraseblocks = { {32 * 1024, 1024} },
.block_erase = SPI_BLOCK_ERASE_52,
}, {
.eraseblocks = { {64 * 1024, 512} },
.block_erase = SPI_BLOCK_ERASE_D8,
}, {
.eraseblocks = { {32 * 1024 * 1024, 1} },
.block_erase = SPI_BLOCK_ERASE_60,
}, {
.eraseblocks = { {32 * 1024 * 1024, 1} },
.block_erase = SPI_BLOCK_ERASE_C7,
}
},
/* TODO: block WP, security register, configuration register */
.printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, /* bit6 is quad enable */
.unlock = SPI_DISABLE_BLOCKPROTECT_BP3_SRWD,
.write = SPI_CHIP_WRITE256,
.read = SPI_CHIP_READ, /* Fast read (0x0B) supported */
.voltage = {2700, 3600},
},
/* The ST M25P05 is a bit of a problem. It has the same ID as the
* ST M25P05-A in RES mode, but supports only 128 byte writes instead
* of 256 byte writes. We rely heavily on the fact that PROBE_SPI_RES1

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@ -531,6 +531,7 @@
#define MACRONIX_MX25U51245G 0x253a
#define MACRONIX_MX25L3235D 0x5E16 /* MX25L3225D/MX25L3235D/MX25L3237D */
#define MACRONIX_MX25L6495F 0x9517
#define MACRONIX_MX77L25650F 0x7519
#define MACRONIX_MX25R3235F 0x2816
#define MACRONIX_MX25R6435F 0x2817