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Intel NIC with parallel flash support

Browse Source 
Tested-by: Maciej Pijanka <maciej.pijanka@gmail.com>

Corresponding to flashrom svn r1297.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested-by: Anton Kochkov <anton.kochkov@gmail.com>
Acked-by: Anton Kochkov <anton.kochkov@gmail.com>
This commit is contained in:
Carl-Daniel Hailfinger 2011-05-08 00:24:18 +00:00
parent 064bbc9f37
commit b713d2e35c
6 changed files with 163 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
Makefile
View File

@ -178,6 +178,9 @@ CONFIG_NICREALTEK ?= yes
# Disable National Semiconductor NICs until support is complete and tested.
CONFIG_NICNATSEMI ?= no
# Always enable Intel NICs for now.
CONFIG_NICINTEL ?= yes
# Always enable SPI on Intel NICs for now.
CONFIG_NICINTEL_SPI ?= yes
@ -297,6 +300,12 @@ PROGRAMMER_OBJS += nicnatsemi.o
NEED_PCI := yes
endif
ifeq ($(CONFIG_NICINTEL), yes)
FEATURE_CFLAGS += -D'CONFIG_NICINTEL=1'
PROGRAMMER_OBJS += nicintel.o
NEED_PCI := yes
endif
ifeq ($(CONFIG_NICINTEL_SPI), yes)
FEATURE_CFLAGS += -D'CONFIG_NICINTEL_SPI=1'
PROGRAMMER_OBJS += nicintel_spi.o

24
flashrom.c
View File

@ -52,7 +52,7 @@ enum programmer programmer = PROGRAMMER_DUMMY;
* if more than one of them is selected. If only one is selected, it is clear
* that the user wants that one to become the default.
*/
#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG+CONFIG_RAYER_SPI+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV > 1
#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG+CONFIG_RAYER_SPI+CONFIG_NICINTEL+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV > 1
#error Please enable either CONFIG_DUMMY or CONFIG_INTERNAL or disable support for all programmers except one.
#endif
enum programmer programmer =
@ -92,6 +92,9 @@ enum programmer programmer =
#if CONFIG_RAYER_SPI == 1
PROGRAMMER_RAYER_SPI
#endif
#if CONFIG_NICINTEL == 1
PROGRAMMER_NICINTEL
#endif
#if CONFIG_NICINTEL_SPI == 1
PROGRAMMER_NICINTEL_SPI
#endif
@ -390,6 +393,25 @@ const struct programmer_entry programmer_table[] = {
},
#endif
#if CONFIG_NICINTEL == 1
{
.name = "nicintel",
.init = nicintel_init,
.shutdown = nicintel_shutdown,
.map_flash_region = fallback_map,
.unmap_flash_region = fallback_unmap,
.chip_readb = nicintel_chip_readb,
.chip_readw = fallback_chip_readw,
.chip_readl = fallback_chip_readl,
.chip_readn = fallback_chip_readn,
.chip_writeb = nicintel_chip_writeb,
.chip_writew = fallback_chip_writew,
.chip_writel = fallback_chip_writel,
.chip_writen = fallback_chip_writen,
.delay = internal_delay,
},
#endif
#if CONFIG_NICINTEL_SPI == 1
{
.name = "nicintel_spi",

109
nicintel.c Normal file
View File

@ -0,0 +1,109 @@
/*
* This file is part of the flashrom project.
*
* Copyright (C) 2011 Carl-Daniel Hailfinger
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* Datasheet: http://download.intel.com/design/network/datashts/82559_Fast_Ethernet_Multifunction_PCI_Cardbus_Controller_Datasheet.pdf */
#include <stdlib.h>
#include "flash.h"
#include "programmer.h"
uint8_t *nicintel_bar;
uint8_t *nicintel_control_bar;
const struct pcidev_status nics_intel[] = {
{PCI_VENDOR_ID_INTEL, 0x1209, NT, "Intel", "8255xER/82551IT Fast Ethernet Controller"},
{PCI_VENDOR_ID_INTEL, 0x1229, NT, "Intel", "82557/8/9/0/1 Ethernet Pro 100"},
{},
};
/* Arbitrary limit, taken from the datasheet I just had lying around.
* 128 kByte on the 82559 device. Or not. Depends on whom you ask.
*/
#define NICINTEL_MEMMAP_SIZE (128 * 1024)
#define NICINTEL_MEMMAP_MASK (NICINTEL_MEMMAP_SIZE - 1)
#define CSR_FCR 0x0c
int nicintel_init(void)
{
uintptr_t addr;
/* Needed only for PCI accesses on some platforms.
* FIXME: Refactor that into get_mem_perms/get_io_perms/get_pci_perms?
*/
get_io_perms();
/* No need to check for errors, pcidev_init() will not return in case
* of errors.
* FIXME: BAR2 is not available if the device uses the CardBus function.
*/
addr = pcidev_init(PCI_BASE_ADDRESS_2, nics_intel);
nicintel_bar = physmap("Intel NIC flash", addr, NICINTEL_MEMMAP_SIZE);
if (nicintel_bar == ERROR_PTR)
goto error_out;
/* FIXME: Using pcidev_dev _will_ cause pretty explosions in the future. */
addr = pcidev_validate(pcidev_dev, PCI_BASE_ADDRESS_0, nics_intel);
/* FIXME: This is not an aligned mapping. Use 4k? */
nicintel_control_bar = physmap("Intel NIC control/status reg", addr, 0x10);
if (nicintel_control_bar == ERROR_PTR)
goto error_out;
/* FIXME: This register is pretty undocumented in all publicly available
* documentation from Intel. Let me quote the complete info we have:
* "Flash Control Register: The Flash Control register allows the CPU to
* enable writes to an external Flash. The Flash Control Register is a
* 32-bit field that allows access to an external Flash device."
* Ah yes, we also know where it is, but we have absolutely _no_ idea
* what we should do with it. Write 0x0001 because we have nothing
* better to do with our time.
*/
pci_rmmio_writew(0x0001, nicintel_control_bar + CSR_FCR);
buses_supported = CHIP_BUSTYPE_PARALLEL;
max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE;
return 0;
error_out:
pci_cleanup(pacc);
release_io_perms();
return 1;
}
int nicintel_shutdown(void)
{
physunmap(nicintel_bar, NICINTEL_MEMMAP_SIZE);
pci_cleanup(pacc);
release_io_perms();
return 0;
}
void nicintel_chip_writeb(uint8_t val, chipaddr addr)
{
pci_mmio_writeb(val, nicintel_bar + (addr & NICINTEL_MEMMAP_MASK));
}
uint8_t nicintel_chip_readb(const chipaddr addr)
{
return pci_mmio_readb(nicintel_bar + (addr & NICINTEL_MEMMAP_MASK));
}

5
print.c
View File

@ -304,6 +304,11 @@ void print_supported(void)
/* FIXME */
printf("RayeR parallel port programmer\n");
#endif
#if CONFIG_NICINTEL == 1
printf("\nSupported devices for the %s programmer:\n",
programmer_table[PROGRAMMER_NICINTEL].name);
print_supported_pcidevs(nics_intel);
#endif
#if CONFIG_NICINTEL_SPI == 1
printf("\nSupported devices for the %s programmer:\n",
programmer_table[PROGRAMMER_NICINTEL_SPI].name);

5
print_wiki.c
View File

@ -247,7 +247,7 @@ static void print_supported_chips_wiki(int cols)
}
/* Not needed for CONFIG_INTERNAL, but for all other PCI-based programmers. */
#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV >= 1
#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_NICINTEL+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV >= 1
static void print_supported_pcidevs_wiki(const struct pcidev_status *devs)
{
int i = 0;
@ -298,6 +298,9 @@ void print_supported_wiki(void)
#if CONFIG_ATAHPT == 1
print_supported_pcidevs_wiki(ata_hpt);
#endif
#if CONFIG_NICINTEL == 1
print_supported_pcidevs_wiki(nics_intel);
#endif
#if CONFIG_NICINTEL_SPI == 1
print_supported_pcidevs_wiki(nics_intel_spi);
#endif

14
programmer.h
View File

@ -67,6 +67,9 @@ enum programmer {
#if CONFIG_RAYER_SPI == 1
PROGRAMMER_RAYER_SPI,
#endif
#if CONFIG_NICINTEL == 1
PROGRAMMER_NICINTEL,
#endif
#if CONFIG_NICINTEL_SPI == 1
PROGRAMMER_NICINTEL_SPI,
#endif
@ -232,7 +235,7 @@ int rpci_write_long(struct pci_dev *dev, int reg, uint32_t data);
#endif
/* print.c */
#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV >= 1
#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_NICINTEL+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV >= 1
void print_supported_pcidevs(const struct pcidev_status *devs);
#endif
@ -420,6 +423,15 @@ uint8_t nicnatsemi_chip_readb(const chipaddr addr);
extern const struct pcidev_status nics_natsemi[];
#endif
/* nicintel.c */
#if CONFIG_NICINTEL == 1
int nicintel_init(void);
int nicintel_shutdown(void);
void nicintel_chip_writeb(uint8_t val, chipaddr addr);
uint8_t nicintel_chip_readb(const chipaddr addr);
extern const struct pcidev_status nics_intel[];
#endif
/* nicintel_spi.c */
#if CONFIG_NICINTEL_SPI == 1
int nicintel_spi_init(void);