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flashchips: add GD25B128E and GD25R128E

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GD25B128E: 3V 128Mbit shipped with QE = 1
https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00594-GD25B128E-Rev1.0.pdf

GD25R128E: GD25Q128E with RPMC feature.
GD25Q128E and GD25R128E share the same datasheet on the flash side.
https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20240729/DS-00480-GD25Q128E-Rev1.3.pdf

Tested on ch347 both models with read write erase and protection.

Change-Id: I14e3c44ebbcc65640042a7719401615b5aa66cc2
Signed-off-by: Victor Lim <vlim@gigadevice.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83967
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Victor Lim 2024-08-17 19:33:01 -07:00 committed by Anastasia Klimchuk
parent 1197f0832d
commit b938411eff
2 changed files with 2 additions and 2 deletions
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2
flashchips.c
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@ -7273,7 +7273,7 @@ const struct flashchip flashchips[] = {
{
.vendor = "GigaDevice",
.name = "GD25Q127C/GD25Q128E",
.name = "GD25Q128E/GD25B128E/GD25R128E/GD25Q127C",
.bustype = BUS_SPI,
.manufacture_id = GIGADEVICE_ID,
.model_id = GIGADEVICE_GD25Q128,

2
include/flashchips.h
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@ -391,7 +391,7 @@
#define GIGADEVICE_GD25Q16 0x4015 /* Same as GD25Q16B (which has OTP) */
#define GIGADEVICE_GD25Q32 0x4016 /* Same as GD25Q32B */
#define GIGADEVICE_GD25Q64 0x4017 /* Same as GD25Q64B */
#define GIGADEVICE_GD25Q128 0x4018 /* Same as GD25Q128B, GD25Q127C, GD25Q128C, and GD25Q128E, can be distinguished by SFDP */
#define GIGADEVICE_GD25Q128 0x4018 /* Same as GD25Q128B, GD25Q127C, GD25Q128C,and GD25Q128E, GD25B128E, GD25R128E can be distinguished by SFDP */
#define GIGADEVICE_GD25Q256D 0x4019
#define GIGADEVICE_GD25VQ21B 0x4212
#define GIGADEVICE_GD25VQ41B 0x4213 /* Same as GD25VQ40C, can be distinguished by SFDP */