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flashchips: Add write-protect support for GD25LQ255E
datasheet: https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20221129/DS-00562-GD25LQ255E-Rev1.1.pdf BUG=b:311336475 TEST=Verified on karis w/o this patch: $ flashrom_tester --flashrom_binary ./flashrom internal Lock_top_quad --> Failed w/ this patch: $ flashrom_tester --flashrom_binary ./flashrom internal Lock_top_quad --> Pass This lock_top_quad test did(copied from partial_lock_test()): * Disable hardware WP so we can modify the protected range. * Then enable software WP so the range is enforced and enable hardware WP so that flashrom does not disable software WP during the operation. * Check that we cannot write to the protected region. * Check that we can write to the non protected region. Change-Id: I1425e931433c00caceaabc6037a79099d6d5eac5 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/79460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
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flashchips.c
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flashchips.c
@ -6557,7 +6557,7 @@ const struct flashchip flashchips[] = {
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.page_size = 256,
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/* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR_EXT2 | FEATURE_4BA,
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.tested = TEST_OK_PREW,
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.tested = TEST_OK_PREWB,
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.probe = PROBE_SPI_RDID,
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.probe_timing = TIMING_ZERO,
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.block_erasers =
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@ -6593,6 +6593,16 @@ const struct flashchip flashchips[] = {
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.write = SPI_CHIP_WRITE256,
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.read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
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.voltage = {1650, 2000},
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.reg_bits =
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{
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.srp = {STATUS1, 7, RW},
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.srl = {STATUS2, 0, RW},
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.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
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.tb = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like TB */
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.sec = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like SEC */
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.cmp = {STATUS2, 6, RW},
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},
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.decode_range = DECODE_RANGE_SPI25,
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},
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{
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