openwrt/flashrom
1
0
Fork 0
mirror of https://review.coreboot.org/flashrom.git synced 2025-04-30 08:23:42 +02:00
Code Issues Releases Wiki Activity

flashchips.c: enable WP for EN25QH32 and EN25QH64

Browse Source 
Split chips:
 * EN25QH32 -> EN25QH32 and EN25QH32B
 * EN25QH64 -> EN25QH64 and EN25QH64A

Unlike older revisions both newly added EN25QH32B and EN25QH64A support
half block (32KiB) erase operation via 0x52 opcode.

Change-Id: I759f0119346235ce0bddc78cde9c461495990c25
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/66213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
This commit is contained in:
Sergii Dmytruk 2022-08-14 20:57:48 +03:00 committed by Anastasia Klimchuk
parent 994de3ae94
commit d899d98859
1 changed files with 96 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

96
flashchips.c
View File

@ -5260,6 +5260,54 @@ const struct flashchip flashchips[] = {
.write = SPI_CHIP_WRITE256,
.read = SPI_CHIP_READ,
.voltage = {2700, 3600},
.reg_bits =
{
.srp = {STATUS1, 7, RW},
.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
.tb = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like TB */
},
.decode_range = DECODE_RANGE_SPI25,
},
{
.vendor = "Eon",
.name = "EN25QH32B",
.bustype = BUS_SPI,
.manufacture_id = EON_ID_NOPREFIX,
.model_id = EON_EN25QH32,
.total_size = 4096,
.page_size = 256,
/* supports SFDP */
/* OTP: 1536B total; enter 0x3A */
/* QPI enable 0x38, disable 0xFF */
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI,
.tested = TEST_OK_PREW,
.probe = PROBE_SPI_RDID,
.probe_timing = TIMING_ZERO,
.block_erasers =
{
{
.eraseblocks = { {4 * 1024, 1024} },
.block_erase = SPI_BLOCK_ERASE_20,
}, {
.eraseblocks = { {32 * 1024, 128} },
.block_erase = SPI_BLOCK_ERASE_52,
}, {
.eraseblocks = { {64 * 1024, 64} },
.block_erase = SPI_BLOCK_ERASE_D8,
}, {
.eraseblocks = { {1024 * 4096, 1} },
.block_erase = SPI_BLOCK_ERASE_60,
}, {
.eraseblocks = { {1024 * 4096, 1} },
.block_erase = SPI_BLOCK_ERASE_C7,
}
},
.printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */
.unlock = spi_disable_blockprotect_bp3_srwd,
.write = SPI_CHIP_WRITE256,
.read = SPI_CHIP_READ,
.voltage = {2700, 3600},
},
{
@ -5298,6 +5346,54 @@ const struct flashchip flashchips[] = {
.write = SPI_CHIP_WRITE256,
.read = SPI_CHIP_READ,
.voltage = {2700, 3600},
.reg_bits =
{
.srp = {STATUS1, 7, RW},
.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
.tb = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like TB */
},
.decode_range = DECODE_RANGE_SPI25_64K_BLOCK,
},
{
.vendor = "Eon",
.name = "EN25QH64A",
.bustype = BUS_SPI,
.manufacture_id = EON_ID_NOPREFIX,
.model_id = EON_EN25QH64,
.total_size = 8192,
.page_size = 256,
/* supports SFDP */
/* OTP: 512B total; enter 0x3A */
/* QPI enable 0x38, disable 0xFF */
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI,
.tested = TEST_OK_PREW,
.probe = PROBE_SPI_RDID,
.probe_timing = TIMING_ZERO,
.block_erasers =
{
{
.eraseblocks = { {4 * 1024, 2048} },
.block_erase = SPI_BLOCK_ERASE_20,
}, {
.eraseblocks = { {32 * 1024, 256} },
.block_erase = SPI_BLOCK_ERASE_52,
}, {
.eraseblocks = { {64 * 1024, 128} },
.block_erase = SPI_BLOCK_ERASE_D8,
}, {
.eraseblocks = { { 8192 * 1024, 1} },
.block_erase = SPI_BLOCK_ERASE_60,
}, {
.eraseblocks = { { 8192 * 1024, 1} },
.block_erase = SPI_BLOCK_ERASE_C7,
}
},
.printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */
.unlock = spi_disable_blockprotect_bp3_srwd,
.write = SPI_CHIP_WRITE256,
.read = SPI_CHIP_READ,
.voltage = {2700, 3600},
},
{