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chipset_enable.c: check return value from rphysmap() call

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Port from the ChromiumOS fork of flashrom.

Change-Id: I8075fe5f80ac0da5280d2f0de6829ed3a2496476
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/46444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Edward O'Callaghan
2020-10-15 19:19:05 +11:00
committed by Edward O'Callaghan
parent c15de25a7c
commit da0825f05f
1 changed files with 2 additions and 0 deletions
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chipset_enable.c
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@@ -1010,6 +1010,8 @@ static int enable_flash_silvermont(struct pci_dev *dev, const char *name)
uint32_t sbase = pci_read_long(dev, 0x54) & 0xfffffe00; uint32_t sbase = pci_read_long(dev, 0x54) & 0xfffffe00;
msg_pdbg("SPI_BASE_ADDRESS = 0x%x\n", sbase); msg_pdbg("SPI_BASE_ADDRESS = 0x%x\n", sbase);
void *spibar = rphysmap("BYT SBASE", sbase, 512); /* Last defined address on Bay Trail is 0x100 */ void *spibar = rphysmap("BYT SBASE", sbase, 512); /* Last defined address on Bay Trail is 0x100 */
if (spibar == ERROR_PTR)
return ERROR_FATAL;
/* Enable Flash Writes. /* Enable Flash Writes.
* Silvermont-based: BCR at SBASE + 0xFC (some bits of BCR are also accessible via BC at IBASE + 0x1C). * Silvermont-based: BCR at SBASE + 0xFC (some bits of BCR are also accessible via BC at IBASE + 0x1C).