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mirror of https://review.coreboot.org/flashrom.git synced 2025-04-27 07:02:34 +02:00

tree/: Make probe_opcode() flashctx argument const

Probing an opcode generally shouldn't involve mutating the flashctx
state and currently no probe_opcode functions do that.

Make the flashctx arg const so that call sites don't need to have a
non-const pointer.

BUG=b:253715389,b:253713774
BRANCH=none
TEST=ninja test

Change-Id: I19e98be50d682de2d2715417f8b7b8c62b871617
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/70030
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nikolai Artemiev 2022-11-28 17:40:56 +11:00 committed by Edward O'Callaghan
parent eda27e4d1b
commit e31d721469
4 changed files with 6 additions and 6 deletions

View File

@ -122,10 +122,10 @@ static int dummy_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsig
emu_data->spi_write_256_chunksize);
}
static bool dummy_spi_probe_opcode(struct flashctx *flash, uint8_t opcode)
static bool dummy_spi_probe_opcode(const struct flashctx *flash, uint8_t opcode)
{
size_t i;
struct emu_data *emu_data = flash->mst->spi.data;
const struct emu_data *emu_data = flash->mst->spi.data;
for (i = 0; i < emu_data->spi_blacklist_size; i++) {
if (emu_data->spi_blacklist[i] == opcode)
return false;

View File

@ -1661,7 +1661,7 @@ static int ich_spi_send_multicommand(const struct flashctx *flash,
return ret;
}
static bool ich_spi_probe_opcode(struct flashctx *flash, uint8_t opcode)
static bool ich_spi_probe_opcode(const struct flashctx *flash, uint8_t opcode)
{
return find_opcode(curopcodes, opcode) >= 0;
}

View File

@ -312,7 +312,7 @@ struct spi_master {
int (*write_256)(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
int (*write_aai)(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
int (*shutdown)(void *data);
bool (*probe_opcode)(struct flashctx *flash, uint8_t opcode);
bool (*probe_opcode)(const struct flashctx *flash, uint8_t opcode);
void *data;
};
@ -322,7 +322,7 @@ int default_spi_send_multicommand(const struct flashctx *flash, struct spi_comma
int default_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);
int default_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
int default_spi_write_aai(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
bool default_spi_probe_opcode(struct flashctx *flash, uint8_t opcode);
bool default_spi_probe_opcode(const struct flashctx *flash, uint8_t opcode);
int register_spi_master(const struct spi_master *mst, void *data);
/* The following enum is needed by ich_descriptor_tool and ich* code as well as in chipset_enable.c. */

2
spi.c
View File

@ -134,7 +134,7 @@ int spi_aai_write(struct flashctx *flash, const uint8_t *buf, unsigned int start
return flash->mst->spi.write_aai(flash, buf, start, len);
}
bool default_spi_probe_opcode(struct flashctx *flash, uint8_t opcode)
bool default_spi_probe_opcode(const struct flashctx *flash, uint8_t opcode)
{
return true;
}