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Add support for RayeR SPIPGM hardware as described in http://rayer.ic.cz/elektro/spipgm.htm
To use the RayeR driver, run flashrom -p rayer_spi -V Known bugs/limitations: - Won't compile/work on non-x86 architectures. - Will always use direct port I/O access. Log follows: flashrom v0.9.2-r1039 on MS-DOS 7 (i686), built with libpci 3.1.5, GCC 4.3.2, little endian Calibrating delay loop... OK. Initializing rayer_bitbang_spi programmer Using port 0x378 as I/O base for parallel port access. ... Probing for Macronix MX25L1605, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 ... Found chip "Macronix MX25L1605" (2048 KB, SPI) at physical address 0xffe00000. ... No operations were specified. Corresponding to flashrom svn r1093. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Martin Rehak <rayer@seznam.cz> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
This commit is contained in:
Carl-Daniel Hailfinger
parent
17e23ac979
commit
e7fdd6e9a1
16
Makefile
16
Makefile
@ -111,8 +111,15 @@ CONFIG_INTERNAL ?= yes
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# Always enable serprog for now. Needs to be disabled on Windows.
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CONFIG_SERPROG ?= yes
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# Bitbanging SPI infrastructure is not used yet.
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# RayeR SPIPGM hardware support
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CONFIG_RAYER_SPI ?= yes
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# Bitbanging SPI infrastructure, default off unless needed.
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ifeq ($(CONFIG_RAYER_SPI), yes)
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override CONFIG_BITBANG_SPI = yes
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else
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CONFIG_BITBANG_SPI ?= no
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endif
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# Always enable 3Com NICs for now.
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CONFIG_NIC3COM ?= yes
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@ -166,6 +173,13 @@ NEED_SERIAL := yes
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NEED_NET := yes
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endif
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ifeq ($(CONFIG_RAYER_SPI), yes)
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FEATURE_CFLAGS += -D'CONFIG_RAYER_SPI=1'
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PROGRAMMER_OBJS += rayer_spi.o
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# Actually, NEED_PCI is wrong. NEED_IOPORT_ACCESS would be more correct.
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NEED_PCI := yes
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endif
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ifeq ($(CONFIG_BITBANG_SPI), yes)
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FEATURE_CFLAGS += -D'CONFIG_BITBANG_SPI=1'
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PROGRAMMER_OBJS += bitbang_spi.o
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14
flash.h
14
flash.h
@ -80,6 +80,9 @@ enum programmer {
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#endif
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#if CONFIG_DEDIPROG == 1
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PROGRAMMER_DEDIPROG,
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#endif
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#if CONFIG_RAYER_SPI == 1
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PROGRAMMER_RAYER_SPI,
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#endif
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PROGRAMMER_INVALID /* This must always be the last entry. */
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};
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@ -129,6 +132,9 @@ void programmer_delay(int usecs);
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enum bitbang_spi_master_type {
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BITBANG_SPI_INVALID = 0, /* This must always be the first entry. */
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#if CONFIG_RAYER_SPI == 1
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BITBANG_SPI_MASTER_RAYER,
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#endif
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};
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struct bitbang_spi_master {
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@ -531,6 +537,11 @@ int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const u
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int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);
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int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);
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/* rayer_spi.c */
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#if CONFIG_RAYER_SPI == 1
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int rayer_spi_init(void);
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#endif
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/* bitbang_spi.c */
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int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod);
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int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);
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@ -649,6 +660,9 @@ enum spi_controller {
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#endif
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#if CONFIG_DEDIPROG == 1
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SPI_CONTROLLER_DEDIPROG,
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#endif
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#if CONFIG_RAYER_SPI == 1
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SPI_CONTROLLER_RAYER,
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#endif
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SPI_CONTROLLER_INVALID /* This must always be the last entry. */
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};
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10
flashrom.8
10
flashrom.8
@ -187,6 +187,9 @@ USB SPI programmer)"
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.sp
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.BR "* buspirate_spi" " (for SPI flash ROMs attached to a Bus Pirate)"
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.sp
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.BR "* rayer_spi" " (for SPI flash ROMs attached to a RayeR parport \
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based programmer)"
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.sp
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Some programmers have optional or mandatory parameters which are described
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in detail in the
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.B PROGRAMMER SPECIFIC INFO
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@ -389,6 +392,10 @@ where
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can be any of
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.BR 30k ", " 125k ", " 250k ", " 1M ", " 2M ", " 2.6M ", " 4M ", " 8M
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(in Hz). The default is the maximum frequency of 8 MHz.
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.TP
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.BR "rayer_spi " programmer
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No parameters defined yet. More information about the hardware is available at
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http://rayer.ic.cz/elektro/spipgm.htm
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.SH EXIT STATUS
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flashrom exits with 0 on success, 1 on most failures but with 2 if /dev/mem
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(/dev/xsvc on Solaris) can not be opened and with 3 if a call to mmap() fails.
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@ -411,6 +418,9 @@ needs PCI configuration space access and raw I/O port access.
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.BR gfxnvidia " and " drkaiser
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need PCI configuration space access and raw memory access.
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.sp
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.B rayer_spi
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needs raw I/O port access.
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.sp
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.B satasii
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needs PCI configuration space read access and raw memory access.
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.sp
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24
flashrom.c
24
flashrom.c
@ -48,7 +48,7 @@ enum programmer programmer = PROGRAMMER_DUMMY;
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* if more than one of them is selected. If only one is selected, it is clear
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* that the user wants that one to become the default.
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*/
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#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG > 1
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#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG+CONFIG_RAYER_SPI > 1
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#error Please enable either CONFIG_DUMMY or CONFIG_INTERNAL or disable support for all programmers except one.
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#endif
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enum programmer programmer =
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@ -86,6 +86,9 @@ enum programmer programmer =
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#if CONFIG_DEDIPROG == 1
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PROGRAMMER_DEDIPROG
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#endif
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#if CONFIG_RAYER_SPI == 1
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PROGRAMMER_RAYER_SPI
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#endif
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;
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#endif
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@ -391,6 +394,25 @@ const struct programmer_entry programmer_table[] = {
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},
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#endif
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#if CONFIG_RAYER_SPI == 1
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{
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.name = "rayer_spi",
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.init = rayer_spi_init,
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.shutdown = noop_shutdown,
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.map_flash_region = fallback_map,
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.unmap_flash_region = fallback_unmap,
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.chip_readb = noop_chip_readb,
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.chip_readw = fallback_chip_readw,
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.chip_readl = fallback_chip_readl,
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.chip_readn = fallback_chip_readn,
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.chip_writeb = noop_chip_writeb,
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.chip_writew = fallback_chip_writew,
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.chip_writel = fallback_chip_writel,
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.chip_writen = fallback_chip_writen,
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.delay = internal_delay,
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},
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#endif
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{}, /* This entry corresponds to PROGRAMMER_INVALID. */
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};
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122
rayer_spi.c
Normal file
122
rayer_spi.c
Normal file
@ -0,0 +1,122 @@
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/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2009,2010 Carl-Daniel Hailfinger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* Driver for the SPIPGM hardware by "RayeR" Martin Rehak.
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* See http://rayer.ic.cz/elektro/spipgm.htm for schematics and instructions.
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*/
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/* This driver uses non-portable direct I/O port accesses which won't work on
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* any non-x86 platform, and even on x86 there is a high chance there will be
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* collisions with any loaded parallel port drivers.
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* The big advantage of direct port I/O is OS independence and speed because
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* most OS parport drivers will perform many unnecessary accesses although
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* this driver just treats the parallel port as a GPIO set.
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*/
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#if defined(__i386__) || defined(__x86_64__)
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#include "flash.h"
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/* We have two sets of pins, out and in. The numbers for both sets are
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* independent and are bitshift values, not real pin numbers.
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*/
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/* Pins for master->slave direction */
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#define SPI_CS_PIN 5
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#define SPI_SCK_PIN 6
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#define SPI_MOSI_PIN 7
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/* Pins for slave->master direction */
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#define SPI_MISO_PIN 6
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static int lpt_iobase;
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/* FIXME: All rayer_bitbang_set_* functions could use caching of the value
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* stored at port lpt_iobase to avoid unnecessary INB. In theory, only one
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* INB(lpt_iobase) would be needed on programmer init to get the initial
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* value.
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*/
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void rayer_bitbang_set_cs(int val)
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{
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uint8_t tmp;
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tmp = INB(lpt_iobase);
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tmp &= ~(1 << SPI_CS_PIN);
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tmp |= (val << SPI_CS_PIN);
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OUTB(tmp, lpt_iobase);
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}
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void rayer_bitbang_set_sck(int val)
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{
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uint8_t tmp;
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tmp = INB(lpt_iobase);
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tmp &= ~(1 << SPI_SCK_PIN);
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tmp |= (val << SPI_SCK_PIN);
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OUTB(tmp, lpt_iobase);
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}
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void rayer_bitbang_set_mosi(int val)
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{
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uint8_t tmp;
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tmp = INB(lpt_iobase);
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tmp &= ~(1 << SPI_MOSI_PIN);
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tmp |= (val << SPI_MOSI_PIN);
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OUTB(tmp, lpt_iobase);
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}
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int rayer_bitbang_get_miso(void)
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{
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uint8_t tmp;
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tmp = INB(lpt_iobase + 1);
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tmp = (tmp >> SPI_MISO_PIN) & 0x1;
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return tmp;
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}
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static const struct bitbang_spi_master bitbang_spi_master_rayer = {
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.type = BITBANG_SPI_MASTER_RAYER,
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.set_cs = rayer_bitbang_set_cs,
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.set_sck = rayer_bitbang_set_sck,
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.set_mosi = rayer_bitbang_set_mosi,
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.get_miso = rayer_bitbang_get_miso,
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};
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int rayer_spi_init(void)
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{
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/* Pick a default value for now. */
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lpt_iobase = 0x378;
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msg_pdbg("Using port 0x%x as I/O base for parallel port access.\n",
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lpt_iobase);
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get_io_perms();
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/* 1 usec halfperiod delay for now. */
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if (bitbang_spi_init(&bitbang_spi_master_rayer, 1))
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return 1;
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buses_supported = CHIP_BUSTYPE_SPI;
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spi_controller = SPI_CONTROLLER_RAYER;
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return 0;
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}
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#else
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#error PCI port I/O access is not supported on this architecture yet.
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#endif
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9
spi.c
9
spi.c
@ -121,6 +121,15 @@ const struct spi_programmer spi_programmer[] = {
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},
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#endif
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#if CONFIG_RAYER_SPI == 1
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{ /* SPI_CONTROLLER_RAYER */
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.command = bitbang_spi_send_command,
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.multicommand = default_spi_send_multicommand,
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.read = bitbang_spi_read,
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.write_256 = bitbang_spi_write_256,
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},
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#endif
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{}, /* This entry corresponds to SPI_CONTROLLER_INVALID. */
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};
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