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flashchips: Enable FEATURE_4BA_EAR_1716 for ISSI chips

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According to their datasheets, ISSI IS25LP256 and IS25WP256 support
both 0xc5/0xc8 and 0x17/0x16 opcodes to write / read their extended
address register. Flashrom will use 0xc5 by default if available,
so adding the FEATURE_4BA_EAR_1716 flag makes no difference for now
(FEATURE_4BA_EAR_C5C8 is included in the already selected FEATURE_4BA
set). It's better to have a comprehensive description of the chips,
though, in case somebody wants to use them in the future with a
master that restricts available opcodes.

Change-Id: I03e4ff825c7742e7ff79b51b75293d53a091d4d4
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/65264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
This commit is contained in:
Nico Huber 2022-06-20 19:32:16 +02:00 committed by Nico Huber
parent d90e2b3e2c
commit e8ce432faa
1 changed files with 4 additions and 2 deletions
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6
flashchips.c
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@ -7469,7 +7469,8 @@ const struct flashchip flashchips[] = {
.page_size = 256,
/* supports SFDP */
/* OTP: 1024B total; read 0x68; write 0x62, erase 0x64, read ID 0x4B */
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA | FEATURE_4BA_ENTER_EAR7,
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP |
FEATURE_4BA | FEATURE_4BA_ENTER_EAR7 | FEATURE_4BA_EAR_1716,
.tested = TEST_OK_PREW,
.probe = probe_spi_rdid,
.probe_timing = TIMING_ZERO,
@ -7644,7 +7645,8 @@ const struct flashchip flashchips[] = {
.page_size = 256,
/* supports SFDP */
/* OTP: 1024B total; read 0x68; write 0x62, erase 0x64, read ID 0x4B */
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA | FEATURE_4BA_ENTER_EAR7,
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP |
FEATURE_4BA | FEATURE_4BA_ENTER_EAR7 | FEATURE_4BA_EAR_1716,
.tested = TEST_OK_PREW,
.probe = probe_spi_rdid,
.probe_timing = TIMING_ZERO,