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it85spi.c: Fix some space/tab trivial style issues

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Change-Id: I9192461281f9e760644a241148f4c5100f76da98
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/64246
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Edward O'Callaghan 2022-05-11 12:30:34 +10:00 committed by Edward O'Callaghan
parent fa2cf255ec
commit e9367e614e
1 changed files with 27 additions and 26 deletions
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53
it85spi.c
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@ -241,53 +241,54 @@ static int it85xx_spi_send_command(const struct flashctx *flash,
struct it85spi_data *data = flash->mst->spi.data; struct it85spi_data *data = flash->mst->spi.data;
it85xx_enter_scratch_rom(data); it85xx_enter_scratch_rom(data);
/* Exit scratch ROM ONLY when programmer shuts down. Otherwise, the /*
* temporary flash state may halt the EC. * Exit scratch ROM ONLY when programmer shuts down. Otherwise, the
*/ * temporary flash state may halt the EC.
*/
#ifdef LPC_IO #ifdef LPC_IO
INDIRECT_A1(data->shm_io_base, (((unsigned long int)data->ce_high) >> 8) & 0xff); INDIRECT_A1(data->shm_io_base, (((unsigned long int)data->ce_high) >> 8) & 0xff);
INDIRECT_WRITE(data->shm_io_base, 0xFF); /* Write anything to this address.*/ INDIRECT_WRITE(data->shm_io_base, 0xFF); /* Write anything to this address.*/
INDIRECT_A1(data->shm_io_base, (((unsigned long int)data->ce_low) >> 8) & 0xff); INDIRECT_A1(data->shm_io_base, (((unsigned long int)data->ce_low) >> 8) & 0xff);
#endif #endif
#ifdef LPC_MEMORY #ifdef LPC_MEMORY
mmio_writeb(0, data->ce_high); mmio_writeb(0, data->ce_high);
#endif #endif
for (i = 0; i < writecnt; ++i) { for (i = 0; i < writecnt; ++i) {
#ifdef LPC_IO #ifdef LPC_IO
INDIRECT_WRITE(data->shm_io_base, writearr[i]); INDIRECT_WRITE(data->shm_io_base, writearr[i]);
#endif #endif
#ifdef LPC_MEMORY #ifdef LPC_MEMORY
mmio_writeb(writearr[i], data->ce_low); mmio_writeb(writearr[i], data->ce_low);
#endif #endif
} }
for (i = 0; i < readcnt; ++i) { for (i = 0; i < readcnt; ++i) {
#ifdef LPC_IO #ifdef LPC_IO
readarr[i] = INDIRECT_READ(data->shm_io_base); readarr[i] = INDIRECT_READ(data->shm_io_base);
#endif #endif
#ifdef LPC_MEMORY #ifdef LPC_MEMORY
readarr[i] = mmio_readb(data->ce_low); readarr[i] = mmio_readb(data->ce_low);
#endif #endif
} }
#ifdef LPC_IO #ifdef LPC_IO
INDIRECT_A1(data->shm_io_base, (((unsigned long int)data->ce_high) >> 8) & 0xff); INDIRECT_A1(data->shm_io_base, (((unsigned long int)data->ce_high) >> 8) & 0xff);
INDIRECT_WRITE(data->shm_io_base, 0xFF); /* Write anything to this address.*/ INDIRECT_WRITE(data->shm_io_base, 0xFF); /* Write anything to this address.*/
#endif #endif
#ifdef LPC_MEMORY #ifdef LPC_MEMORY
mmio_writeb(0, data->ce_high); mmio_writeb(0, data->ce_high);
#endif #endif
return 0; return 0;
} }
static const struct spi_master spi_master_it85xx = { static const struct spi_master spi_master_it85xx = {
.max_data_read = 64, .max_data_read = 64,
.max_data_write = 64, .max_data_write = 64,
.command = it85xx_spi_send_command, .command = it85xx_spi_send_command,
.multicommand = default_spi_send_multicommand, .multicommand = default_spi_send_multicommand,
.read = default_spi_read, .read = default_spi_read,
.write_256 = default_spi_write_256, .write_256 = default_spi_write_256,
.write_aai = default_spi_write_aai, .write_aai = default_spi_write_aai,
.shutdown = it85xx_shutdown, .shutdown = it85xx_shutdown,
}; };