mirror of
https://review.coreboot.org/flashrom.git
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dummyflasher: add SR2 and SR3 emulation harness
Prepare everything for emulating SR2 and SR3 for chips that have it.
This is needed for accessing SRP1 and WPS bits which are involved in
write protection. The emulated register doesn't affect anything yet
and will be tested by write-protection tests.
TEST=check how input value affects status registers of emulated chip
flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x12 |
grep 'Initial status register'
flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x1234 |
grep 'Initial status register'
flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x123456 |
grep 'Initial status register'
Mind that at this point there are no chips that emulate more than one
status register.
Change-Id: I177ae3f068f03380f5b3941d9996a07205672e59
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
This commit is contained in:
Sergii Dmytruk
Anastasia Klimchuk
parent
c829a48e19
commit
fa2cf255ec
122
dummyflasher.c
122
dummyflasher.c
@ -13,6 +13,7 @@
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* GNU General Public License for more details.
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*/
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#include <assert.h>
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#include <string.h>
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#include <stdlib.h>
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#include <stdio.h>
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@ -40,9 +41,14 @@ struct emu_data {
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enum emu_chip emu_chip;
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char *emu_persistent_image;
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unsigned int emu_chip_size;
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/* Note: W25Q128FV doesn't change value of SR2 if it's not provided, but
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* even its previous generations do, so don't forget to update
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* WRSR code on enabling WRSR_EXT for more chips. */
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bool emu_wrsr_ext;
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int erase_to_zero;
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int emu_modified; /* is the image modified since reading it? */
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uint8_t emu_status;
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uint8_t emu_status[3];
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uint8_t emu_status_len; /* number of emulated status registers */
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/* If "freq" parameter is passed in from command line, commands will delay
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* for this period before returning. */
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unsigned long int delay_us;
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@ -158,6 +164,15 @@ static void dummy_chip_readn(const struct flashctx *flash, uint8_t *buf, const c
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return;
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}
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static uint8_t get_reg_ro_bit_mask(enum flash_reg reg)
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{
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/* Whoever adds a new register must not forget to update this function
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or at least shouldn't use it incorrectly. */
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assert(reg == STATUS1 || reg == STATUS2 || reg == STATUS3);
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return reg == STATUS1 ? SPI_SR_WIP : 0;
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}
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static int emulate_spi_chip_response(unsigned int writecnt,
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unsigned int readcnt,
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const unsigned char *writearr,
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@ -165,6 +180,8 @@ static int emulate_spi_chip_response(unsigned int writecnt,
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struct emu_data *data)
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{
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unsigned int offs, i, toread;
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uint8_t ro_bits;
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bool wrsr_ext;
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static int unsigned aai_offs;
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const unsigned char sst25vf040_rems_response[2] = {0xbf, 0x44};
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const unsigned char sst25vf032b_rems_response[2] = {0xbf, 0x4a};
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@ -194,7 +211,7 @@ static int emulate_spi_chip_response(unsigned int writecnt,
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}
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}
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if (data->emu_max_aai_size && (data->emu_status & SPI_SR_AAI)) {
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if (data->emu_max_aai_size && (data->emu_status[0] & SPI_SR_AAI)) {
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if (writearr[0] != JEDEC_AAI_WORD_PROGRAM &&
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writearr[0] != JEDEC_WRDI &&
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writearr[0] != JEDEC_RDSR) {
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@ -304,21 +321,72 @@ static int emulate_spi_chip_response(unsigned int writecnt,
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}
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break;
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case JEDEC_RDSR:
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memset(readarr, data->emu_status, readcnt);
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memset(readarr, data->emu_status[0], readcnt);
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break;
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case JEDEC_RDSR2:
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if (data->emu_status_len >= 2)
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memset(readarr, data->emu_status[1], readcnt);
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break;
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case JEDEC_RDSR3:
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if (data->emu_status_len >= 3)
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memset(readarr, data->emu_status[2], readcnt);
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break;
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/* FIXME: this should be chip-specific. */
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case JEDEC_EWSR:
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case JEDEC_WREN:
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data->emu_status |= SPI_SR_WEL;
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data->emu_status[0] |= SPI_SR_WEL;
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break;
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case JEDEC_WRSR:
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if (!(data->emu_status & SPI_SR_WEL)) {
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if (!(data->emu_status[0] & SPI_SR_WEL)) {
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msg_perr("WRSR attempted, but WEL is 0!\n");
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break;
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}
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wrsr_ext = (writecnt == 3 && data->emu_wrsr_ext);
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/* FIXME: add some reasonable simulation of the busy flag */
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data->emu_status = writearr[1] & ~SPI_SR_WIP;
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msg_pdbg2("WRSR wrote 0x%02x.\n", data->emu_status);
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ro_bits = get_reg_ro_bit_mask(STATUS1);
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data->emu_status[0] &= ro_bits;
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data->emu_status[0] |= writearr[1] & ~ro_bits;
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if (wrsr_ext) {
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ro_bits = get_reg_ro_bit_mask(STATUS2);
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data->emu_status[1] &= ro_bits;
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data->emu_status[1] |= writearr[2] & ~ro_bits;
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}
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if (wrsr_ext)
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msg_pdbg2("WRSR wrote 0x%02x%02x.\n", data->emu_status[1], data->emu_status[0]);
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else
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msg_pdbg2("WRSR wrote 0x%02x.\n", data->emu_status[0]);
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break;
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case JEDEC_WRSR2:
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if (data->emu_status_len < 2)
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break;
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if (!(data->emu_status[0] & SPI_SR_WEL)) {
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msg_perr("WRSR2 attempted, but WEL is 0!\n");
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break;
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}
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ro_bits = get_reg_ro_bit_mask(STATUS2);
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data->emu_status[1] &= ro_bits;
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data->emu_status[1] |= (writearr[1] & ~ro_bits);
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msg_pdbg2("WRSR2 wrote 0x%02x.\n", data->emu_status[1]);
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break;
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case JEDEC_WRSR3:
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if (data->emu_status_len < 3)
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break;
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if (!(data->emu_status[0] & SPI_SR_WEL)) {
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msg_perr("WRSR3 attempted, but WEL is 0!\n");
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break;
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}
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ro_bits = get_reg_ro_bit_mask(STATUS3);
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data->emu_status[2] &= ro_bits;
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data->emu_status[2] |= (writearr[1] & ~ro_bits);
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msg_pdbg2("WRSR3 wrote 0x%02x.\n", data->emu_status[2]);
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break;
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case JEDEC_READ:
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offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
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@ -367,7 +435,7 @@ static int emulate_spi_chip_response(unsigned int writecnt,
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case JEDEC_AAI_WORD_PROGRAM:
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if (!data->emu_max_aai_size)
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break;
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if (!(data->emu_status & SPI_SR_AAI)) {
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if (!(data->emu_status[0] & SPI_SR_AAI)) {
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if (writecnt < JEDEC_AAI_WORD_PROGRAM_OUTSIZE) {
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msg_perr("Initial AAI WORD PROGRAM size too "
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"short!\n");
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@ -378,7 +446,7 @@ static int emulate_spi_chip_response(unsigned int writecnt,
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"long!\n");
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return 1;
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}
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data->emu_status |= SPI_SR_AAI;
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data->emu_status[0] |= SPI_SR_AAI;
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aai_offs = writearr[1] << 16 | writearr[2] << 8 |
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writearr[3];
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/* Truncate to emu_chip_size. */
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@ -403,7 +471,7 @@ static int emulate_spi_chip_response(unsigned int writecnt,
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break;
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case JEDEC_WRDI:
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if (data->emu_max_aai_size)
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data->emu_status &= ~SPI_SR_AAI;
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data->emu_status[0] &= ~SPI_SR_AAI;
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break;
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case JEDEC_SE:
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if (!data->emu_jedec_se_size)
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@ -531,7 +599,7 @@ static int emulate_spi_chip_response(unsigned int writecnt,
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break;
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}
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if (writearr[0] != JEDEC_WREN && writearr[0] != JEDEC_EWSR)
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data->emu_status &= ~SPI_SR_WEL;
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data->emu_status[0] &= ~SPI_SR_WEL;
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return 0;
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}
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@ -811,6 +879,7 @@ static int init_data(struct emu_data *data, enum chipbustype *dummy_buses_suppor
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data->emu_chip_size = 128 * 1024;
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data->emu_max_byteprogram_size = 128;
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data->emu_max_aai_size = 0;
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data->emu_status_len = 1;
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data->emu_jedec_se_size = 0;
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data->emu_jedec_be_52_size = 0;
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data->emu_jedec_be_d8_size = 32 * 1024;
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@ -824,6 +893,7 @@ static int init_data(struct emu_data *data, enum chipbustype *dummy_buses_suppor
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data->emu_chip_size = 512 * 1024;
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data->emu_max_byteprogram_size = 1;
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data->emu_max_aai_size = 0;
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data->emu_status_len = 1;
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data->emu_jedec_se_size = 4 * 1024;
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data->emu_jedec_be_52_size = 32 * 1024;
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data->emu_jedec_be_d8_size = 0;
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@ -837,6 +907,7 @@ static int init_data(struct emu_data *data, enum chipbustype *dummy_buses_suppor
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data->emu_chip_size = 4 * 1024 * 1024;
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data->emu_max_byteprogram_size = 1;
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data->emu_max_aai_size = 2;
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data->emu_status_len = 1;
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data->emu_jedec_se_size = 4 * 1024;
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data->emu_jedec_be_52_size = 32 * 1024;
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data->emu_jedec_be_d8_size = 64 * 1024;
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@ -850,6 +921,7 @@ static int init_data(struct emu_data *data, enum chipbustype *dummy_buses_suppor
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data->emu_chip_size = 8 * 1024 * 1024;
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data->emu_max_byteprogram_size = 256;
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data->emu_max_aai_size = 0;
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data->emu_status_len = 1;
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data->emu_jedec_se_size = 4 * 1024;
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data->emu_jedec_be_52_size = 32 * 1024;
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data->emu_jedec_be_d8_size = 64 * 1024;
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@ -863,6 +935,7 @@ static int init_data(struct emu_data *data, enum chipbustype *dummy_buses_suppor
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data->emu_chip_size = 16 * 1024 * 1024;
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data->emu_max_byteprogram_size = 256;
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data->emu_max_aai_size = 0;
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data->emu_status_len = 1;
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data->emu_jedec_se_size = 4 * 1024;
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data->emu_jedec_be_52_size = 32 * 1024;
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data->emu_jedec_be_d8_size = 64 * 1024;
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@ -884,6 +957,7 @@ static int init_data(struct emu_data *data, enum chipbustype *dummy_buses_suppor
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data->emu_chip_size = size;
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data->emu_max_byteprogram_size = 256;
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data->emu_max_aai_size = 0;
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data->emu_status_len = 1;
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data->emu_jedec_se_size = 4 * 1024;
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data->emu_jedec_be_52_size = 32 * 1024;
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data->emu_jedec_be_d8_size = 64 * 1024;
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@ -918,8 +992,10 @@ static int init_data(struct emu_data *data, enum chipbustype *dummy_buses_suppor
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status = extract_programmer_param("spi_status");
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if (status) {
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unsigned int emu_status;
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errno = 0;
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data->emu_status = strtoul(status, &endptr, 0);
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emu_status = strtoul(status, &endptr, 0);
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if (errno != 0 || status == endptr) {
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free(status);
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msg_perr("Error: initial status register specified, "
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@ -927,8 +1003,26 @@ static int init_data(struct emu_data *data, enum chipbustype *dummy_buses_suppor
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return 1;
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}
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free(status);
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msg_pdbg("Initial status register is set to 0x%02x.\n",
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data->emu_status);
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data->emu_status[0] = emu_status;
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data->emu_status[1] = emu_status >> 8;
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data->emu_status[2] = emu_status >> 16;
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if (data->emu_status_len == 3) {
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msg_pdbg("Initial status registers:\n"
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"\tSR1 is set to 0x%02x\n"
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"\tSR2 is set to 0x%02x\n"
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"\tSR3 is set to 0x%02x\n",
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data->emu_status[0], data->emu_status[1], data->emu_status[2]);
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} else if (data->emu_status_len == 2) {
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msg_pdbg("Initial status registers:\n"
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"\tSR1 is set to 0x%02x\n"
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"\tSR2 is set to 0x%02x\n",
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data->emu_status[0], data->emu_status[1]);
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} else {
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msg_pdbg("Initial status register is set to 0x%02x.\n",
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data->emu_status[0]);
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}
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}
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data->flashchip_contents = malloc(data->emu_chip_size);
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@ -816,7 +816,10 @@ You can specify the initial content of the chip's status register with the
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.sp
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syntax where
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.B content
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is an 8-bit hexadecimal value.
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is a hexadecimal value of up to 24 bits. For example, 0x332211 assigns 0x11 to
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SR1, 0x22 to SR2 and 0x33 to SR3. Shorter value is padded to 24 bits with
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zeroes on the left. See datasheet for chosen chip for details about the
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registers content.
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.SS
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.BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel", " nicintel_eeprom"\
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, " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii"\
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