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Prepare everything for emulating SR2 and SR3 for chips that have it. This is needed for accessing SRP1 and WPS bits which are involved in write protection. The emulated register doesn't affect anything yet and will be tested by write-protection tests. TEST=check how input value affects status registers of emulated chip flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x12 | grep 'Initial status register' flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x1234 | grep 'Initial status register' flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x123456 | grep 'Initial status register' Mind that at this point there are no chips that emulate more than one status register. Change-Id: I177ae3f068f03380f5b3941d9996a07205672e59 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
1165 lines
34 KiB
C
1165 lines
34 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2009,2010 Carl-Daniel Hailfinger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <assert.h>
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#include <string.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <ctype.h>
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#include <errno.h>
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#include <sys/types.h>
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#include <sys/stat.h>
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#include "flash.h"
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#include "chipdrivers.h"
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#include "programmer.h"
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#include "flashchips.h"
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#include "spi.h"
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enum emu_chip {
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EMULATE_NONE,
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EMULATE_ST_M25P10_RES,
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EMULATE_SST_SST25VF040_REMS,
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EMULATE_SST_SST25VF032B,
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EMULATE_MACRONIX_MX25L6436,
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EMULATE_WINBOND_W25Q128FV,
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EMULATE_VARIABLE_SIZE,
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};
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struct emu_data {
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enum emu_chip emu_chip;
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char *emu_persistent_image;
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unsigned int emu_chip_size;
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/* Note: W25Q128FV doesn't change value of SR2 if it's not provided, but
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* even its previous generations do, so don't forget to update
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* WRSR code on enabling WRSR_EXT for more chips. */
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bool emu_wrsr_ext;
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int erase_to_zero;
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int emu_modified; /* is the image modified since reading it? */
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uint8_t emu_status[3];
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uint8_t emu_status_len; /* number of emulated status registers */
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/* If "freq" parameter is passed in from command line, commands will delay
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* for this period before returning. */
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unsigned long int delay_us;
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unsigned int emu_max_byteprogram_size;
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unsigned int emu_max_aai_size;
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unsigned int emu_jedec_se_size;
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unsigned int emu_jedec_be_52_size;
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unsigned int emu_jedec_be_d8_size;
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unsigned int emu_jedec_ce_60_size;
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unsigned int emu_jedec_ce_c7_size;
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unsigned char spi_blacklist[256];
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unsigned char spi_ignorelist[256];
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unsigned int spi_blacklist_size;
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unsigned int spi_ignorelist_size;
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unsigned int spi_write_256_chunksize;
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uint8_t *flashchip_contents;
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};
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/* A legit complete SFDP table based on the MX25L6436E (rev. 1.8) datasheet. */
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static const uint8_t sfdp_table[] = {
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0x53, 0x46, 0x44, 0x50, // @0x00: SFDP signature
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0x00, 0x01, 0x01, 0xFF, // @0x04: revision 1.0, 2 headers
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0x00, 0x00, 0x01, 0x09, // @0x08: JEDEC SFDP header rev. 1.0, 9 DW long
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0x1C, 0x00, 0x00, 0xFF, // @0x0C: PTP0 = 0x1C (instead of 0x30)
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0xC2, 0x00, 0x01, 0x04, // @0x10: Macronix header rev. 1.0, 4 DW long
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0x48, 0x00, 0x00, 0xFF, // @0x14: PTP1 = 0x48 (instead of 0x60)
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0xFF, 0xFF, 0xFF, 0xFF, // @0x18: hole.
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0xE5, 0x20, 0xC9, 0xFF, // @0x1C: SFDP parameter table start
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0xFF, 0xFF, 0xFF, 0x03, // @0x20
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0x00, 0xFF, 0x08, 0x6B, // @0x24
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0x08, 0x3B, 0x00, 0xFF, // @0x28
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0xEE, 0xFF, 0xFF, 0xFF, // @0x2C
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0xFF, 0xFF, 0x00, 0x00, // @0x30
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0xFF, 0xFF, 0x00, 0xFF, // @0x34
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0x0C, 0x20, 0x0F, 0x52, // @0x38
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0x10, 0xD8, 0x00, 0xFF, // @0x3C: SFDP parameter table end
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0xFF, 0xFF, 0xFF, 0xFF, // @0x40: hole.
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0xFF, 0xFF, 0xFF, 0xFF, // @0x44: hole.
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0x00, 0x36, 0x00, 0x27, // @0x48: Macronix parameter table start
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0xF4, 0x4F, 0xFF, 0xFF, // @0x4C
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0xD9, 0xC8, 0xFF, 0xFF, // @0x50
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0xFF, 0xFF, 0xFF, 0xFF, // @0x54: Macronix parameter table end
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};
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static void *dummy_map(const char *descr, uintptr_t phys_addr, size_t len)
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{
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msg_pspew("%s: Mapping %s, 0x%zx bytes at 0x%0*" PRIxPTR "\n",
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__func__, descr, len, PRIxPTR_WIDTH, phys_addr);
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return (void *)phys_addr;
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}
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static void dummy_unmap(void *virt_addr, size_t len)
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{
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msg_pspew("%s: Unmapping 0x%zx bytes at %p\n", __func__, len, virt_addr);
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}
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static int dummy_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len)
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{
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struct emu_data *emu_data = flash->mst->spi.data;
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return spi_write_chunked(flash, buf, start, len,
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emu_data->spi_write_256_chunksize);
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}
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static void dummy_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
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{
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msg_pspew("%s: addr=0x%" PRIxPTR ", val=0x%02x\n", __func__, addr, val);
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}
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static void dummy_chip_writew(const struct flashctx *flash, uint16_t val, chipaddr addr)
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{
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msg_pspew("%s: addr=0x%" PRIxPTR ", val=0x%04x\n", __func__, addr, val);
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}
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static void dummy_chip_writel(const struct flashctx *flash, uint32_t val, chipaddr addr)
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{
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msg_pspew("%s: addr=0x%" PRIxPTR ", val=0x%08x\n", __func__, addr, val);
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}
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static void dummy_chip_writen(const struct flashctx *flash, const uint8_t *buf, chipaddr addr, size_t len)
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{
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size_t i;
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msg_pspew("%s: addr=0x%" PRIxPTR ", len=0x%zx, writing data (hex):", __func__, addr, len);
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for (i = 0; i < len; i++) {
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if ((i % 16) == 0)
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msg_pspew("\n");
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msg_pspew("%02x ", buf[i]);
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}
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}
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static uint8_t dummy_chip_readb(const struct flashctx *flash, const chipaddr addr)
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{
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msg_pspew("%s: addr=0x%" PRIxPTR ", returning 0xff\n", __func__, addr);
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return 0xff;
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}
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static uint16_t dummy_chip_readw(const struct flashctx *flash, const chipaddr addr)
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{
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msg_pspew("%s: addr=0x%" PRIxPTR ", returning 0xffff\n", __func__, addr);
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return 0xffff;
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}
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static uint32_t dummy_chip_readl(const struct flashctx *flash, const chipaddr addr)
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{
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msg_pspew("%s: addr=0x%" PRIxPTR ", returning 0xffffffff\n", __func__, addr);
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return 0xffffffff;
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}
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static void dummy_chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len)
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{
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msg_pspew("%s: addr=0x%" PRIxPTR ", len=0x%zx, returning array of 0xff\n", __func__, addr, len);
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memset(buf, 0xff, len);
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return;
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}
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static uint8_t get_reg_ro_bit_mask(enum flash_reg reg)
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{
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/* Whoever adds a new register must not forget to update this function
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or at least shouldn't use it incorrectly. */
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assert(reg == STATUS1 || reg == STATUS2 || reg == STATUS3);
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return reg == STATUS1 ? SPI_SR_WIP : 0;
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}
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static int emulate_spi_chip_response(unsigned int writecnt,
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unsigned int readcnt,
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const unsigned char *writearr,
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unsigned char *readarr,
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struct emu_data *data)
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{
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unsigned int offs, i, toread;
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uint8_t ro_bits;
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bool wrsr_ext;
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static int unsigned aai_offs;
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const unsigned char sst25vf040_rems_response[2] = {0xbf, 0x44};
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const unsigned char sst25vf032b_rems_response[2] = {0xbf, 0x4a};
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const unsigned char mx25l6436_rems_response[2] = {0xc2, 0x16};
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const unsigned char w25q128fv_rems_response[2] = {0xef, 0x17};
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if (writecnt == 0) {
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msg_perr("No command sent to the chip!\n");
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return 1;
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}
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/* spi_blacklist has precedence over spi_ignorelist. */
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for (i = 0; i < data->spi_blacklist_size; i++) {
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if (writearr[0] == data->spi_blacklist[i]) {
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msg_pdbg("Refusing blacklisted SPI command 0x%02x\n",
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data->spi_blacklist[i]);
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return SPI_INVALID_OPCODE;
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}
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}
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for (i = 0; i < data->spi_ignorelist_size; i++) {
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if (writearr[0] == data->spi_ignorelist[i]) {
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msg_cdbg("Ignoring ignorelisted SPI command 0x%02x\n",
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data->spi_ignorelist[i]);
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/* Return success because the command does not fail,
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* it is simply ignored.
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*/
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return 0;
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}
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}
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if (data->emu_max_aai_size && (data->emu_status[0] & SPI_SR_AAI)) {
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if (writearr[0] != JEDEC_AAI_WORD_PROGRAM &&
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writearr[0] != JEDEC_WRDI &&
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writearr[0] != JEDEC_RDSR) {
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msg_perr("Forbidden opcode (0x%02x) attempted during "
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"AAI sequence!\n", writearr[0]);
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return 0;
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}
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}
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switch (writearr[0]) {
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case JEDEC_RES:
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if (writecnt < JEDEC_RES_OUTSIZE)
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break;
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/* offs calculation is only needed for SST chips which treat RES like REMS. */
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offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
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offs += writecnt - JEDEC_REMS_OUTSIZE;
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switch (data->emu_chip) {
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case EMULATE_ST_M25P10_RES:
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if (readcnt > 0)
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memset(readarr, 0x10, readcnt);
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break;
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case EMULATE_SST_SST25VF040_REMS:
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for (i = 0; i < readcnt; i++)
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readarr[i] = sst25vf040_rems_response[(offs + i) % 2];
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break;
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case EMULATE_SST_SST25VF032B:
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for (i = 0; i < readcnt; i++)
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readarr[i] = sst25vf032b_rems_response[(offs + i) % 2];
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break;
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case EMULATE_MACRONIX_MX25L6436:
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if (readcnt > 0)
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memset(readarr, 0x16, readcnt);
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break;
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case EMULATE_WINBOND_W25Q128FV:
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if (readcnt > 0)
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memset(readarr, 0x17, readcnt);
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break;
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default: /* ignore */
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break;
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}
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break;
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case JEDEC_REMS:
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/* REMS response has wraparound and uses an address parameter. */
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if (writecnt < JEDEC_REMS_OUTSIZE)
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break;
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offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
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offs += writecnt - JEDEC_REMS_OUTSIZE;
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switch (data->emu_chip) {
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case EMULATE_SST_SST25VF040_REMS:
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for (i = 0; i < readcnt; i++)
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readarr[i] = sst25vf040_rems_response[(offs + i) % 2];
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break;
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case EMULATE_SST_SST25VF032B:
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for (i = 0; i < readcnt; i++)
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readarr[i] = sst25vf032b_rems_response[(offs + i) % 2];
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break;
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case EMULATE_MACRONIX_MX25L6436:
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for (i = 0; i < readcnt; i++)
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readarr[i] = mx25l6436_rems_response[(offs + i) % 2];
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break;
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case EMULATE_WINBOND_W25Q128FV:
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for (i = 0; i < readcnt; i++)
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readarr[i] = w25q128fv_rems_response[(offs + i) % 2];
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break;
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default: /* ignore */
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break;
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}
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break;
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case JEDEC_RDID:
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switch (data->emu_chip) {
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case EMULATE_SST_SST25VF032B:
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if (readcnt > 0)
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readarr[0] = 0xbf;
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if (readcnt > 1)
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readarr[1] = 0x25;
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if (readcnt > 2)
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readarr[2] = 0x4a;
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break;
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case EMULATE_MACRONIX_MX25L6436:
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if (readcnt > 0)
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readarr[0] = 0xc2;
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if (readcnt > 1)
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readarr[1] = 0x20;
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if (readcnt > 2)
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readarr[2] = 0x17;
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break;
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case EMULATE_WINBOND_W25Q128FV:
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if (readcnt > 0)
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readarr[0] = 0xef;
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if (readcnt > 1)
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readarr[1] = 0x40;
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if (readcnt > 2)
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readarr[2] = 0x18;
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break;
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case EMULATE_VARIABLE_SIZE:
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if (readcnt > 0)
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readarr[0] = (PROGMANUF_ID >> 8) & 0xff;
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if (readcnt > 1)
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readarr[1] = PROGMANUF_ID & 0xff;
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if (readcnt > 2)
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readarr[2] = (PROGDEV_ID >> 8) & 0xff;
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if (readcnt > 3)
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readarr[3] = PROGDEV_ID & 0xff;
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break;
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default: /* ignore */
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break;
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}
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break;
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case JEDEC_RDSR:
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memset(readarr, data->emu_status[0], readcnt);
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break;
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case JEDEC_RDSR2:
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if (data->emu_status_len >= 2)
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memset(readarr, data->emu_status[1], readcnt);
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break;
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case JEDEC_RDSR3:
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if (data->emu_status_len >= 3)
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memset(readarr, data->emu_status[2], readcnt);
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break;
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/* FIXME: this should be chip-specific. */
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case JEDEC_EWSR:
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case JEDEC_WREN:
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data->emu_status[0] |= SPI_SR_WEL;
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break;
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case JEDEC_WRSR:
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if (!(data->emu_status[0] & SPI_SR_WEL)) {
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msg_perr("WRSR attempted, but WEL is 0!\n");
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break;
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}
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wrsr_ext = (writecnt == 3 && data->emu_wrsr_ext);
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/* FIXME: add some reasonable simulation of the busy flag */
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ro_bits = get_reg_ro_bit_mask(STATUS1);
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data->emu_status[0] &= ro_bits;
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data->emu_status[0] |= writearr[1] & ~ro_bits;
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if (wrsr_ext) {
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ro_bits = get_reg_ro_bit_mask(STATUS2);
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data->emu_status[1] &= ro_bits;
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data->emu_status[1] |= writearr[2] & ~ro_bits;
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}
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if (wrsr_ext)
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msg_pdbg2("WRSR wrote 0x%02x%02x.\n", data->emu_status[1], data->emu_status[0]);
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else
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msg_pdbg2("WRSR wrote 0x%02x.\n", data->emu_status[0]);
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break;
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case JEDEC_WRSR2:
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if (data->emu_status_len < 2)
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break;
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if (!(data->emu_status[0] & SPI_SR_WEL)) {
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msg_perr("WRSR2 attempted, but WEL is 0!\n");
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break;
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}
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ro_bits = get_reg_ro_bit_mask(STATUS2);
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data->emu_status[1] &= ro_bits;
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data->emu_status[1] |= (writearr[1] & ~ro_bits);
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msg_pdbg2("WRSR2 wrote 0x%02x.\n", data->emu_status[1]);
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break;
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case JEDEC_WRSR3:
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if (data->emu_status_len < 3)
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break;
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if (!(data->emu_status[0] & SPI_SR_WEL)) {
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msg_perr("WRSR3 attempted, but WEL is 0!\n");
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break;
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}
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ro_bits = get_reg_ro_bit_mask(STATUS3);
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data->emu_status[2] &= ro_bits;
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data->emu_status[2] |= (writearr[1] & ~ro_bits);
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msg_pdbg2("WRSR3 wrote 0x%02x.\n", data->emu_status[2]);
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break;
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case JEDEC_READ:
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offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
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/* Truncate to emu_chip_size. */
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offs %= data->emu_chip_size;
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if (readcnt > 0)
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memcpy(readarr, data->flashchip_contents + offs, readcnt);
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break;
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case JEDEC_READ_4BA:
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offs = writearr[1] << 24 | writearr[2] << 16 | writearr[3] << 8 | writearr[4];
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/* Truncate to emu_chip_size. */
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offs %= data->emu_chip_size;
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if (readcnt > 0)
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memcpy(readarr, data->flashchip_contents + offs, readcnt);
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break;
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case JEDEC_BYTE_PROGRAM:
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offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
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/* Truncate to emu_chip_size. */
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offs %= data->emu_chip_size;
|
|
if (writecnt < 5) {
|
|
msg_perr("BYTE PROGRAM size too short!\n");
|
|
return 1;
|
|
}
|
|
if (writecnt - 4 > data->emu_max_byteprogram_size) {
|
|
msg_perr("Max BYTE PROGRAM size exceeded!\n");
|
|
return 1;
|
|
}
|
|
memcpy(data->flashchip_contents + offs, writearr + 4, writecnt - 4);
|
|
data->emu_modified = 1;
|
|
break;
|
|
case JEDEC_BYTE_PROGRAM_4BA:
|
|
offs = writearr[1] << 24 | writearr[2] << 16 | writearr[3] << 8 | writearr[4];
|
|
/* Truncate to emu_chip_size. */
|
|
offs %= data->emu_chip_size;
|
|
if (writecnt < 6) {
|
|
msg_perr("BYTE PROGRAM size too short!\n");
|
|
return 1;
|
|
}
|
|
if (writecnt - 5 > data->emu_max_byteprogram_size) {
|
|
msg_perr("Max BYTE PROGRAM size exceeded!\n");
|
|
return 1;
|
|
}
|
|
memcpy(data->flashchip_contents + offs, writearr + 5, writecnt - 5);
|
|
data->emu_modified = 1;
|
|
break;
|
|
case JEDEC_AAI_WORD_PROGRAM:
|
|
if (!data->emu_max_aai_size)
|
|
break;
|
|
if (!(data->emu_status[0] & SPI_SR_AAI)) {
|
|
if (writecnt < JEDEC_AAI_WORD_PROGRAM_OUTSIZE) {
|
|
msg_perr("Initial AAI WORD PROGRAM size too "
|
|
"short!\n");
|
|
return 1;
|
|
}
|
|
if (writecnt > JEDEC_AAI_WORD_PROGRAM_OUTSIZE) {
|
|
msg_perr("Initial AAI WORD PROGRAM size too "
|
|
"long!\n");
|
|
return 1;
|
|
}
|
|
data->emu_status[0] |= SPI_SR_AAI;
|
|
aai_offs = writearr[1] << 16 | writearr[2] << 8 |
|
|
writearr[3];
|
|
/* Truncate to emu_chip_size. */
|
|
aai_offs %= data->emu_chip_size;
|
|
memcpy(data->flashchip_contents + aai_offs, writearr + 4, 2);
|
|
aai_offs += 2;
|
|
} else {
|
|
if (writecnt < JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE) {
|
|
msg_perr("Continuation AAI WORD PROGRAM size "
|
|
"too short!\n");
|
|
return 1;
|
|
}
|
|
if (writecnt > JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE) {
|
|
msg_perr("Continuation AAI WORD PROGRAM size "
|
|
"too long!\n");
|
|
return 1;
|
|
}
|
|
memcpy(data->flashchip_contents + aai_offs, writearr + 1, 2);
|
|
aai_offs += 2;
|
|
}
|
|
data->emu_modified = 1;
|
|
break;
|
|
case JEDEC_WRDI:
|
|
if (data->emu_max_aai_size)
|
|
data->emu_status[0] &= ~SPI_SR_AAI;
|
|
break;
|
|
case JEDEC_SE:
|
|
if (!data->emu_jedec_se_size)
|
|
break;
|
|
if (writecnt != JEDEC_SE_OUTSIZE) {
|
|
msg_perr("SECTOR ERASE 0x20 outsize invalid!\n");
|
|
return 1;
|
|
}
|
|
if (readcnt != JEDEC_SE_INSIZE) {
|
|
msg_perr("SECTOR ERASE 0x20 insize invalid!\n");
|
|
return 1;
|
|
}
|
|
offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
|
|
if (offs & (data->emu_jedec_se_size - 1))
|
|
msg_pdbg("Unaligned SECTOR ERASE 0x20: 0x%x\n", offs);
|
|
offs &= ~(data->emu_jedec_se_size - 1);
|
|
memset(data->flashchip_contents + offs, 0xff, data->emu_jedec_se_size);
|
|
data->emu_modified = 1;
|
|
break;
|
|
case JEDEC_BE_52:
|
|
if (!data->emu_jedec_be_52_size)
|
|
break;
|
|
if (writecnt != JEDEC_BE_52_OUTSIZE) {
|
|
msg_perr("BLOCK ERASE 0x52 outsize invalid!\n");
|
|
return 1;
|
|
}
|
|
if (readcnt != JEDEC_BE_52_INSIZE) {
|
|
msg_perr("BLOCK ERASE 0x52 insize invalid!\n");
|
|
return 1;
|
|
}
|
|
offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
|
|
if (offs & (data->emu_jedec_be_52_size - 1))
|
|
msg_pdbg("Unaligned BLOCK ERASE 0x52: 0x%x\n", offs);
|
|
offs &= ~(data->emu_jedec_be_52_size - 1);
|
|
memset(data->flashchip_contents + offs, 0xff, data->emu_jedec_be_52_size);
|
|
data->emu_modified = 1;
|
|
break;
|
|
case JEDEC_BE_D8:
|
|
if (!data->emu_jedec_be_d8_size)
|
|
break;
|
|
if (writecnt != JEDEC_BE_D8_OUTSIZE) {
|
|
msg_perr("BLOCK ERASE 0xd8 outsize invalid!\n");
|
|
return 1;
|
|
}
|
|
if (readcnt != JEDEC_BE_D8_INSIZE) {
|
|
msg_perr("BLOCK ERASE 0xd8 insize invalid!\n");
|
|
return 1;
|
|
}
|
|
offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
|
|
if (offs & (data->emu_jedec_be_d8_size - 1))
|
|
msg_pdbg("Unaligned BLOCK ERASE 0xd8: 0x%x\n", offs);
|
|
offs &= ~(data->emu_jedec_be_d8_size - 1);
|
|
memset(data->flashchip_contents + offs, 0xff, data->emu_jedec_be_d8_size);
|
|
data->emu_modified = 1;
|
|
break;
|
|
case JEDEC_CE_60:
|
|
if (!data->emu_jedec_ce_60_size)
|
|
break;
|
|
if (writecnt != JEDEC_CE_60_OUTSIZE) {
|
|
msg_perr("CHIP ERASE 0x60 outsize invalid!\n");
|
|
return 1;
|
|
}
|
|
if (readcnt != JEDEC_CE_60_INSIZE) {
|
|
msg_perr("CHIP ERASE 0x60 insize invalid!\n");
|
|
return 1;
|
|
}
|
|
/* JEDEC_CE_60_OUTSIZE is 1 (no address) -> no offset. */
|
|
/* emu_jedec_ce_60_size is emu_chip_size. */
|
|
memset(data->flashchip_contents, 0xff, data->emu_jedec_ce_60_size);
|
|
data->emu_modified = 1;
|
|
break;
|
|
case JEDEC_CE_C7:
|
|
if (!data->emu_jedec_ce_c7_size)
|
|
break;
|
|
if (writecnt != JEDEC_CE_C7_OUTSIZE) {
|
|
msg_perr("CHIP ERASE 0xc7 outsize invalid!\n");
|
|
return 1;
|
|
}
|
|
if (readcnt != JEDEC_CE_C7_INSIZE) {
|
|
msg_perr("CHIP ERASE 0xc7 insize invalid!\n");
|
|
return 1;
|
|
}
|
|
/* JEDEC_CE_C7_OUTSIZE is 1 (no address) -> no offset. */
|
|
/* emu_jedec_ce_c7_size is emu_chip_size. */
|
|
memset(data->flashchip_contents, 0xff, data->emu_jedec_ce_c7_size);
|
|
data->emu_modified = 1;
|
|
break;
|
|
case JEDEC_SFDP:
|
|
if (data->emu_chip != EMULATE_MACRONIX_MX25L6436)
|
|
break;
|
|
if (writecnt < 4)
|
|
break;
|
|
offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
|
|
|
|
/* SFDP expects one dummy byte after the address. */
|
|
if (writecnt == 4) {
|
|
/* The dummy byte was not written, make sure it is read instead.
|
|
* Shifting and shortening the read array does achieve this goal.
|
|
*/
|
|
readarr++;
|
|
readcnt--;
|
|
} else {
|
|
/* The response is shifted if more than 5 bytes are written, because SFDP data is
|
|
* already shifted out by the chip while those superfluous bytes are written. */
|
|
offs += writecnt - 5;
|
|
}
|
|
|
|
/* The SFDP spec implies that the start address of an SFDP read may be truncated to fit in the
|
|
* SFDP table address space, i.e. the start address may be wrapped around at SFDP table size.
|
|
* This is a reasonable implementation choice in hardware because it saves a few gates. */
|
|
if (offs >= sizeof(sfdp_table)) {
|
|
msg_pdbg("Wrapping the start address around the SFDP table boundary (using 0x%x "
|
|
"instead of 0x%x).\n", (unsigned int)(offs % sizeof(sfdp_table)), offs);
|
|
offs %= sizeof(sfdp_table);
|
|
}
|
|
toread = min(sizeof(sfdp_table) - offs, readcnt);
|
|
memcpy(readarr, sfdp_table + offs, toread);
|
|
if (toread < readcnt)
|
|
msg_pdbg("Crossing the SFDP table boundary in a single "
|
|
"continuous chunk produces undefined results "
|
|
"after that point.\n");
|
|
break;
|
|
default:
|
|
/* No special response. */
|
|
break;
|
|
}
|
|
if (writearr[0] != JEDEC_WREN && writearr[0] != JEDEC_EWSR)
|
|
data->emu_status[0] &= ~SPI_SR_WEL;
|
|
return 0;
|
|
}
|
|
|
|
static int dummy_spi_send_command(const struct flashctx *flash, unsigned int writecnt,
|
|
unsigned int readcnt,
|
|
const unsigned char *writearr,
|
|
unsigned char *readarr)
|
|
{
|
|
unsigned int i;
|
|
struct emu_data *emu_data = flash->mst->spi.data;
|
|
if (!emu_data) {
|
|
msg_perr("No data in flash context!\n");
|
|
return 1;
|
|
}
|
|
|
|
msg_pspew("%s:", __func__);
|
|
|
|
msg_pspew(" writing %u bytes:", writecnt);
|
|
for (i = 0; i < writecnt; i++)
|
|
msg_pspew(" 0x%02x", writearr[i]);
|
|
|
|
/* Response for unknown commands and missing chip is 0xff. */
|
|
memset(readarr, 0xff, readcnt);
|
|
switch (emu_data->emu_chip) {
|
|
case EMULATE_ST_M25P10_RES:
|
|
case EMULATE_SST_SST25VF040_REMS:
|
|
case EMULATE_SST_SST25VF032B:
|
|
case EMULATE_MACRONIX_MX25L6436:
|
|
case EMULATE_WINBOND_W25Q128FV:
|
|
case EMULATE_VARIABLE_SIZE:
|
|
if (emulate_spi_chip_response(writecnt, readcnt, writearr,
|
|
readarr, emu_data)) {
|
|
msg_pdbg("Invalid command sent to flash chip!\n");
|
|
return 1;
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
msg_pspew(" reading %u bytes:", readcnt);
|
|
for (i = 0; i < readcnt; i++)
|
|
msg_pspew(" 0x%02x", readarr[i]);
|
|
msg_pspew("\n");
|
|
|
|
programmer_delay((writecnt + readcnt) * emu_data->delay_us);
|
|
return 0;
|
|
}
|
|
|
|
static int dummy_shutdown(void *data)
|
|
{
|
|
msg_pspew("%s\n", __func__);
|
|
struct emu_data *emu_data = (struct emu_data *)data;
|
|
if (emu_data->emu_chip != EMULATE_NONE) {
|
|
if (emu_data->emu_persistent_image && emu_data->emu_modified) {
|
|
msg_pdbg("Writing %s\n", emu_data->emu_persistent_image);
|
|
write_buf_to_file(emu_data->flashchip_contents,
|
|
emu_data->emu_chip_size,
|
|
emu_data->emu_persistent_image);
|
|
}
|
|
free(emu_data->emu_persistent_image);
|
|
free(emu_data->flashchip_contents);
|
|
}
|
|
free(data);
|
|
return 0;
|
|
}
|
|
|
|
static const struct spi_master spi_master_dummyflasher = {
|
|
.features = SPI_MASTER_4BA,
|
|
.max_data_read = MAX_DATA_READ_UNLIMITED,
|
|
.max_data_write = MAX_DATA_UNSPECIFIED,
|
|
.command = dummy_spi_send_command,
|
|
.multicommand = default_spi_send_multicommand,
|
|
.read = default_spi_read,
|
|
.write_256 = dummy_spi_write_256,
|
|
.write_aai = default_spi_write_aai,
|
|
};
|
|
|
|
static const struct par_master par_master_dummyflasher = {
|
|
.chip_readb = dummy_chip_readb,
|
|
.chip_readw = dummy_chip_readw,
|
|
.chip_readl = dummy_chip_readl,
|
|
.chip_readn = dummy_chip_readn,
|
|
.chip_writeb = dummy_chip_writeb,
|
|
.chip_writew = dummy_chip_writew,
|
|
.chip_writel = dummy_chip_writel,
|
|
.chip_writen = dummy_chip_writen,
|
|
};
|
|
|
|
static int init_data(struct emu_data *data, enum chipbustype *dummy_buses_supported)
|
|
{
|
|
|
|
char *bustext = NULL;
|
|
char *tmp = NULL;
|
|
unsigned int i;
|
|
char *endptr;
|
|
char *status = NULL;
|
|
int size = -1; /* size for VARIABLE_SIZE chip device */
|
|
|
|
bustext = extract_programmer_param("bus");
|
|
msg_pdbg("Requested buses are: %s\n", bustext ? bustext : "default");
|
|
if (!bustext)
|
|
bustext = strdup("parallel+lpc+fwh+spi");
|
|
/* Convert the parameters to lowercase. */
|
|
tolower_string(bustext);
|
|
|
|
*dummy_buses_supported = BUS_NONE;
|
|
if (strstr(bustext, "parallel")) {
|
|
*dummy_buses_supported |= BUS_PARALLEL;
|
|
msg_pdbg("Enabling support for %s flash.\n", "parallel");
|
|
}
|
|
if (strstr(bustext, "lpc")) {
|
|
*dummy_buses_supported |= BUS_LPC;
|
|
msg_pdbg("Enabling support for %s flash.\n", "LPC");
|
|
}
|
|
if (strstr(bustext, "fwh")) {
|
|
*dummy_buses_supported |= BUS_FWH;
|
|
msg_pdbg("Enabling support for %s flash.\n", "FWH");
|
|
}
|
|
if (strstr(bustext, "spi")) {
|
|
*dummy_buses_supported |= BUS_SPI;
|
|
msg_pdbg("Enabling support for %s flash.\n", "SPI");
|
|
}
|
|
if (*dummy_buses_supported == BUS_NONE)
|
|
msg_pdbg("Support for all flash bus types disabled.\n");
|
|
free(bustext);
|
|
|
|
tmp = extract_programmer_param("spi_write_256_chunksize");
|
|
if (tmp) {
|
|
data->spi_write_256_chunksize = strtoul(tmp, &endptr, 0);
|
|
if (*endptr != '\0' || data->spi_write_256_chunksize < 1) {
|
|
msg_perr("invalid spi_write_256_chunksize\n");
|
|
free(tmp);
|
|
return 1;
|
|
}
|
|
}
|
|
free(tmp);
|
|
|
|
tmp = extract_programmer_param("spi_blacklist");
|
|
if (tmp) {
|
|
i = strlen(tmp);
|
|
if (!strncmp(tmp, "0x", 2)) {
|
|
i -= 2;
|
|
memmove(tmp, tmp + 2, i + 1);
|
|
}
|
|
if ((i > 512) || (i % 2)) {
|
|
msg_perr("Invalid SPI command blacklist length\n");
|
|
free(tmp);
|
|
return 1;
|
|
}
|
|
data->spi_blacklist_size = i / 2;
|
|
for (i = 0; i < data->spi_blacklist_size * 2; i++) {
|
|
if (!isxdigit((unsigned char)tmp[i])) {
|
|
msg_perr("Invalid char \"%c\" in SPI command "
|
|
"blacklist\n", tmp[i]);
|
|
free(tmp);
|
|
return 1;
|
|
}
|
|
}
|
|
for (i = 0; i < data->spi_blacklist_size; i++) {
|
|
unsigned int tmp2;
|
|
/* SCNx8 is apparently not supported by MSVC (and thus
|
|
* MinGW), so work around it with an extra variable
|
|
*/
|
|
sscanf(tmp + i * 2, "%2x", &tmp2);
|
|
data->spi_blacklist[i] = (uint8_t)tmp2;
|
|
}
|
|
msg_pdbg("SPI blacklist is ");
|
|
for (i = 0; i < data->spi_blacklist_size; i++)
|
|
msg_pdbg("%02x ", data->spi_blacklist[i]);
|
|
msg_pdbg(", size %u\n", data->spi_blacklist_size);
|
|
}
|
|
free(tmp);
|
|
|
|
tmp = extract_programmer_param("spi_ignorelist");
|
|
if (tmp) {
|
|
i = strlen(tmp);
|
|
if (!strncmp(tmp, "0x", 2)) {
|
|
i -= 2;
|
|
memmove(tmp, tmp + 2, i + 1);
|
|
}
|
|
if ((i > 512) || (i % 2)) {
|
|
msg_perr("Invalid SPI command ignorelist length\n");
|
|
free(tmp);
|
|
return 1;
|
|
}
|
|
data->spi_ignorelist_size = i / 2;
|
|
for (i = 0; i < data->spi_ignorelist_size * 2; i++) {
|
|
if (!isxdigit((unsigned char)tmp[i])) {
|
|
msg_perr("Invalid char \"%c\" in SPI command "
|
|
"ignorelist\n", tmp[i]);
|
|
free(tmp);
|
|
return 1;
|
|
}
|
|
}
|
|
for (i = 0; i < data->spi_ignorelist_size; i++) {
|
|
unsigned int tmp2;
|
|
/* SCNx8 is apparently not supported by MSVC (and thus
|
|
* MinGW), so work around it with an extra variable
|
|
*/
|
|
sscanf(tmp + i * 2, "%2x", &tmp2);
|
|
data->spi_ignorelist[i] = (uint8_t)tmp2;
|
|
}
|
|
msg_pdbg("SPI ignorelist is ");
|
|
for (i = 0; i < data->spi_ignorelist_size; i++)
|
|
msg_pdbg("%02x ", data->spi_ignorelist[i]);
|
|
msg_pdbg(", size %u\n", data->spi_ignorelist_size);
|
|
}
|
|
free(tmp);
|
|
|
|
/* frequency to emulate in Hz (default), KHz, or MHz */
|
|
tmp = extract_programmer_param("freq");
|
|
if (tmp) {
|
|
unsigned long int freq;
|
|
char *units = tmp;
|
|
char *end = tmp + strlen(tmp);
|
|
|
|
errno = 0;
|
|
freq = strtoul(tmp, &units, 0);
|
|
if (errno) {
|
|
msg_perr("Invalid frequency \"%s\", %s\n",
|
|
tmp, strerror(errno));
|
|
free(tmp);
|
|
return 1;
|
|
}
|
|
|
|
if ((units > tmp) && (units < end)) {
|
|
int units_valid = 0;
|
|
|
|
if (units < end - 3) {
|
|
;
|
|
} else if (units == end - 2) {
|
|
if (!strcasecmp(units, "hz"))
|
|
units_valid = 1;
|
|
} else if (units == end - 3) {
|
|
if (!strcasecmp(units, "khz")) {
|
|
freq *= 1000;
|
|
units_valid = 1;
|
|
} else if (!strcasecmp(units, "mhz")) {
|
|
freq *= 1000000;
|
|
units_valid = 1;
|
|
}
|
|
}
|
|
|
|
if (!units_valid) {
|
|
msg_perr("Invalid units: %s\n", units);
|
|
free(tmp);
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
/* Assume we only work with bytes and transfer at 1 bit/Hz */
|
|
data->delay_us = (1000000 * 8) / freq;
|
|
}
|
|
free(tmp);
|
|
|
|
tmp = extract_programmer_param("size");
|
|
if (tmp) {
|
|
size = strtol(tmp, NULL, 10);
|
|
if (size <= 0 || (size % 1024 != 0)) {
|
|
msg_perr("%s: Chip size is not a multiple of 1024: %s\n",
|
|
__func__, tmp);
|
|
free(tmp);
|
|
return 1;
|
|
}
|
|
free(tmp);
|
|
}
|
|
|
|
tmp = extract_programmer_param("emulate");
|
|
if (!tmp) {
|
|
msg_pdbg("Not emulating any flash chip.\n");
|
|
/* Nothing else to do. */
|
|
return 0;
|
|
}
|
|
|
|
if (!strcmp(tmp, "M25P10.RES")) {
|
|
data->emu_chip = EMULATE_ST_M25P10_RES;
|
|
data->emu_chip_size = 128 * 1024;
|
|
data->emu_max_byteprogram_size = 128;
|
|
data->emu_max_aai_size = 0;
|
|
data->emu_status_len = 1;
|
|
data->emu_jedec_se_size = 0;
|
|
data->emu_jedec_be_52_size = 0;
|
|
data->emu_jedec_be_d8_size = 32 * 1024;
|
|
data->emu_jedec_ce_60_size = 0;
|
|
data->emu_jedec_ce_c7_size = data->emu_chip_size;
|
|
msg_pdbg("Emulating ST M25P10.RES SPI flash chip (RES, page "
|
|
"write)\n");
|
|
}
|
|
if (!strcmp(tmp, "SST25VF040.REMS")) {
|
|
data->emu_chip = EMULATE_SST_SST25VF040_REMS;
|
|
data->emu_chip_size = 512 * 1024;
|
|
data->emu_max_byteprogram_size = 1;
|
|
data->emu_max_aai_size = 0;
|
|
data->emu_status_len = 1;
|
|
data->emu_jedec_se_size = 4 * 1024;
|
|
data->emu_jedec_be_52_size = 32 * 1024;
|
|
data->emu_jedec_be_d8_size = 0;
|
|
data->emu_jedec_ce_60_size = data->emu_chip_size;
|
|
data->emu_jedec_ce_c7_size = 0;
|
|
msg_pdbg("Emulating SST SST25VF040.REMS SPI flash chip (REMS, "
|
|
"byte write)\n");
|
|
}
|
|
if (!strcmp(tmp, "SST25VF032B")) {
|
|
data->emu_chip = EMULATE_SST_SST25VF032B;
|
|
data->emu_chip_size = 4 * 1024 * 1024;
|
|
data->emu_max_byteprogram_size = 1;
|
|
data->emu_max_aai_size = 2;
|
|
data->emu_status_len = 1;
|
|
data->emu_jedec_se_size = 4 * 1024;
|
|
data->emu_jedec_be_52_size = 32 * 1024;
|
|
data->emu_jedec_be_d8_size = 64 * 1024;
|
|
data->emu_jedec_ce_60_size = data->emu_chip_size;
|
|
data->emu_jedec_ce_c7_size = data->emu_chip_size;
|
|
msg_pdbg("Emulating SST SST25VF032B SPI flash chip (RDID, AAI "
|
|
"write)\n");
|
|
}
|
|
if (!strcmp(tmp, "MX25L6436")) {
|
|
data->emu_chip = EMULATE_MACRONIX_MX25L6436;
|
|
data->emu_chip_size = 8 * 1024 * 1024;
|
|
data->emu_max_byteprogram_size = 256;
|
|
data->emu_max_aai_size = 0;
|
|
data->emu_status_len = 1;
|
|
data->emu_jedec_se_size = 4 * 1024;
|
|
data->emu_jedec_be_52_size = 32 * 1024;
|
|
data->emu_jedec_be_d8_size = 64 * 1024;
|
|
data->emu_jedec_ce_60_size = data->emu_chip_size;
|
|
data->emu_jedec_ce_c7_size = data->emu_chip_size;
|
|
msg_pdbg("Emulating Macronix MX25L6436 SPI flash chip (RDID, "
|
|
"SFDP)\n");
|
|
}
|
|
if (!strcmp(tmp, "W25Q128FV")) {
|
|
data->emu_chip = EMULATE_WINBOND_W25Q128FV;
|
|
data->emu_chip_size = 16 * 1024 * 1024;
|
|
data->emu_max_byteprogram_size = 256;
|
|
data->emu_max_aai_size = 0;
|
|
data->emu_status_len = 1;
|
|
data->emu_jedec_se_size = 4 * 1024;
|
|
data->emu_jedec_be_52_size = 32 * 1024;
|
|
data->emu_jedec_be_d8_size = 64 * 1024;
|
|
data->emu_jedec_ce_60_size = data->emu_chip_size;
|
|
data->emu_jedec_ce_c7_size = data->emu_chip_size;
|
|
msg_pdbg("Emulating Winbond W25Q128FV SPI flash chip (RDID)\n");
|
|
}
|
|
|
|
/* The name of variable-size virtual chip. A 4 MiB flash example:
|
|
* flashrom -p dummy:emulate=VARIABLE_SIZE,size=4194304
|
|
*/
|
|
if (!strcmp(tmp, "VARIABLE_SIZE")) {
|
|
if (size == -1) {
|
|
msg_perr("%s: the size parameter is not given.\n", __func__);
|
|
free(tmp);
|
|
return 1;
|
|
}
|
|
data->emu_chip = EMULATE_VARIABLE_SIZE;
|
|
data->emu_chip_size = size;
|
|
data->emu_max_byteprogram_size = 256;
|
|
data->emu_max_aai_size = 0;
|
|
data->emu_status_len = 1;
|
|
data->emu_jedec_se_size = 4 * 1024;
|
|
data->emu_jedec_be_52_size = 32 * 1024;
|
|
data->emu_jedec_be_d8_size = 64 * 1024;
|
|
data->emu_jedec_ce_60_size = data->emu_chip_size;
|
|
data->emu_jedec_ce_c7_size = data->emu_chip_size;
|
|
msg_pdbg("Emulating generic SPI flash chip (size=%d bytes)\n",
|
|
data->emu_chip_size);
|
|
}
|
|
|
|
if (data->emu_chip == EMULATE_NONE) {
|
|
msg_perr("Invalid chip specified for emulation: %s\n", tmp);
|
|
free(tmp);
|
|
return 1;
|
|
}
|
|
free(tmp);
|
|
|
|
/* Should emulated flash erase to zero (yes/no)? */
|
|
tmp = extract_programmer_param("erase_to_zero");
|
|
if (tmp) {
|
|
if (!strcmp(tmp, "yes")) {
|
|
msg_pdbg("Emulated chip will erase to 0x00\n");
|
|
data->erase_to_zero = 1;
|
|
} else if (!strcmp(tmp, "no")) {
|
|
msg_pdbg("Emulated chip will erase to 0xff\n");
|
|
} else {
|
|
msg_perr("erase_to_zero can be \"yes\" or \"no\"\n");
|
|
free(tmp);
|
|
return 1;
|
|
}
|
|
}
|
|
free(tmp);
|
|
|
|
status = extract_programmer_param("spi_status");
|
|
if (status) {
|
|
unsigned int emu_status;
|
|
|
|
errno = 0;
|
|
emu_status = strtoul(status, &endptr, 0);
|
|
if (errno != 0 || status == endptr) {
|
|
free(status);
|
|
msg_perr("Error: initial status register specified, "
|
|
"but the value could not be converted.\n");
|
|
return 1;
|
|
}
|
|
free(status);
|
|
|
|
data->emu_status[0] = emu_status;
|
|
data->emu_status[1] = emu_status >> 8;
|
|
data->emu_status[2] = emu_status >> 16;
|
|
|
|
if (data->emu_status_len == 3) {
|
|
msg_pdbg("Initial status registers:\n"
|
|
"\tSR1 is set to 0x%02x\n"
|
|
"\tSR2 is set to 0x%02x\n"
|
|
"\tSR3 is set to 0x%02x\n",
|
|
data->emu_status[0], data->emu_status[1], data->emu_status[2]);
|
|
} else if (data->emu_status_len == 2) {
|
|
msg_pdbg("Initial status registers:\n"
|
|
"\tSR1 is set to 0x%02x\n"
|
|
"\tSR2 is set to 0x%02x\n",
|
|
data->emu_status[0], data->emu_status[1]);
|
|
} else {
|
|
msg_pdbg("Initial status register is set to 0x%02x.\n",
|
|
data->emu_status[0]);
|
|
}
|
|
}
|
|
|
|
data->flashchip_contents = malloc(data->emu_chip_size);
|
|
if (!data->flashchip_contents) {
|
|
msg_perr("Out of memory!\n");
|
|
return 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dummy_init(void)
|
|
{
|
|
struct stat image_stat;
|
|
|
|
struct emu_data *data = calloc(1, sizeof(*data));
|
|
if (!data) {
|
|
msg_perr("Out of memory!\n");
|
|
return 1;
|
|
}
|
|
data->emu_chip = EMULATE_NONE;
|
|
data->delay_us = 0;
|
|
data->spi_write_256_chunksize = 256;
|
|
|
|
msg_pspew("%s\n", __func__);
|
|
|
|
enum chipbustype dummy_buses_supported;
|
|
if (init_data(data, &dummy_buses_supported)) {
|
|
free(data);
|
|
return 1;
|
|
}
|
|
|
|
if (data->emu_chip == EMULATE_NONE) {
|
|
msg_pdbg("Not emulating any flash chip.\n");
|
|
/* Nothing else to do. */
|
|
goto dummy_init_out;
|
|
}
|
|
|
|
msg_pdbg("Filling fake flash chip with 0x%02x, size %i\n",
|
|
data->erase_to_zero ? 0x00 : 0xff, data->emu_chip_size);
|
|
memset(data->flashchip_contents, data->erase_to_zero ? 0x00 : 0xff, data->emu_chip_size);
|
|
|
|
/* Will be freed by shutdown function if necessary. */
|
|
data->emu_persistent_image = extract_programmer_param("image");
|
|
if (!data->emu_persistent_image) {
|
|
/* Nothing else to do. */
|
|
goto dummy_init_out;
|
|
}
|
|
/* We will silently (in default verbosity) ignore the file if it does not exist (yet) or the size does
|
|
* not match the emulated chip. */
|
|
if (!stat(data->emu_persistent_image, &image_stat)) {
|
|
msg_pdbg("Found persistent image %s, %jd B ",
|
|
data->emu_persistent_image, (intmax_t)image_stat.st_size);
|
|
if ((uintmax_t)image_stat.st_size == data->emu_chip_size) {
|
|
msg_pdbg("matches.\n");
|
|
msg_pdbg("Reading %s\n", data->emu_persistent_image);
|
|
if (read_buf_from_file(data->flashchip_contents, data->emu_chip_size,
|
|
data->emu_persistent_image)) {
|
|
msg_perr("Unable to read %s\n", data->emu_persistent_image);
|
|
free(data->emu_persistent_image);
|
|
free(data->flashchip_contents);
|
|
free(data);
|
|
return 1;
|
|
}
|
|
} else {
|
|
msg_pdbg("doesn't match.\n");
|
|
}
|
|
}
|
|
|
|
dummy_init_out:
|
|
if (register_shutdown(dummy_shutdown, data)) {
|
|
free(data->emu_persistent_image);
|
|
free(data->flashchip_contents);
|
|
free(data);
|
|
return 1;
|
|
}
|
|
if (dummy_buses_supported & BUS_NONSPI)
|
|
register_par_master(&par_master_dummyflasher,
|
|
dummy_buses_supported & BUS_NONSPI,
|
|
data);
|
|
if (dummy_buses_supported & BUS_SPI)
|
|
register_spi_master(&spi_master_dummyflasher, data);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int probe_variable_size(struct flashctx *flash)
|
|
{
|
|
unsigned int i;
|
|
const struct emu_data *emu_data = flash->mst->spi.data;
|
|
|
|
/* Skip the probing if we don't emulate this chip. */
|
|
if (!emu_data || emu_data->emu_chip != EMULATE_VARIABLE_SIZE)
|
|
return 0;
|
|
|
|
/*
|
|
* This will break if one day flashctx becomes read-only.
|
|
* Once that happens, we need to have special hacks in functions:
|
|
*
|
|
* erase_and_write_flash() in flashrom.c
|
|
* read_flash_to_file()
|
|
* handle_romentries()
|
|
* ...
|
|
*
|
|
* Search "total_size * 1024" in code.
|
|
*/
|
|
flash->chip->total_size = emu_data->emu_chip_size / 1024;
|
|
msg_cdbg("%s: set flash->total_size to %dK bytes.\n", __func__,
|
|
flash->chip->total_size);
|
|
|
|
if (emu_data->erase_to_zero)
|
|
flash->chip->feature_bits |= FEATURE_ERASED_ZERO;
|
|
|
|
/* Update the first count of each of the block_erasers. */
|
|
for (i = 0; i < NUM_ERASEFUNCTIONS; i++) {
|
|
struct block_eraser *eraser = &flash->chip->block_erasers[i];
|
|
if (!eraser->block_erase)
|
|
break;
|
|
|
|
eraser->eraseblocks[0].count = 1;
|
|
eraser->eraseblocks[0].size = emu_data->emu_chip_size;
|
|
msg_cdbg("%s: eraser.size=%d, .count=%d\n",
|
|
__func__, eraser->eraseblocks[0].size,
|
|
eraser->eraseblocks[0].count);
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
|
|
const struct programmer_entry programmer_dummy = {
|
|
.name = "dummy",
|
|
.type = OTHER,
|
|
/* FIXME */
|
|
.devs.note = "Dummy device, does nothing and logs all accesses\n",
|
|
.init = dummy_init,
|
|
.map_flash_region = dummy_map,
|
|
.unmap_flash_region = dummy_unmap,
|
|
.delay = internal_delay,
|
|
};
|