mirror of
https://review.coreboot.org/flashrom.git
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Register Parallel/LPC/FWH programmers the same way SPI programmers are registered
All programmers are now calling programmer registration functions and direct manipulations of buses_supported are not needed/possible anymore. Note: Programmers without parallel/LPC/FWH chip support should not call register_par_programmer(). Additional fixes: Set max_rom_decode.parallel for drkaiser. Remove abuse of programmer_map_flash_region in it85spi. Annotate several FIXMEs in it85spi. Corresponding to flashrom svn r1463. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
This commit is contained in:
Carl-Daniel Hailfinger
parent
f382e352ac
commit
eaacd2d4e7
16
atahpt.c
16
atahpt.c
@ -40,6 +40,17 @@ const struct pcidev_status ata_hpt[] = {
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{},
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};
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static const struct par_programmer par_programmer_atahpt = {
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.chip_readb = atahpt_chip_readb,
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.chip_readw = fallback_chip_readw,
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.chip_readl = fallback_chip_readl,
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.chip_readn = fallback_chip_readn,
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.chip_writeb = atahpt_chip_writeb,
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.chip_writew = fallback_chip_writew,
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.chip_writel = fallback_chip_writel,
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.chip_writen = fallback_chip_writen,
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};
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static int atahpt_shutdown(void *data)
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{
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/* Flash access is disabled automatically by PCI restore. */
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@ -61,10 +72,11 @@ int atahpt_init(void)
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reg32 |= (1 << 24);
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rpci_write_long(pcidev_dev, REG_FLASH_ACCESS, reg32);
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buses_supported = BUS_PARALLEL;
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if (register_shutdown(atahpt_shutdown, NULL))
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return 1;
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register_par_programmer(&par_programmer_atahpt, BUS_PARALLEL);
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return 0;
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}
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@ -425,7 +425,7 @@ int it8705f_write_enable(uint8_t port)
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/* Check if at least one flash segment is enabled. */
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if (tmp & 0xf0) {
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/* The IT8705F will respond to LPC cycles and translate them. */
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buses_supported = BUS_PARALLEL;
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internal_buses_supported = BUS_PARALLEL;
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/* Flash ROM I/F Writes Enable */
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tmp |= 0x04;
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msg_pdbg("Enabling IT8705F flash ROM interface write.\n");
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@ -213,7 +213,7 @@ static int enable_flash_piix4(struct pci_dev *dev, const char *name)
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uint16_t old, new;
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uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
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buses_supported = BUS_PARALLEL;
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internal_buses_supported = BUS_PARALLEL;
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old = pci_read_word(dev, xbcs);
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@ -303,7 +303,7 @@ static int enable_flash_ich_4e(struct pci_dev *dev, const char *name)
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* FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and
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* FB_DEC_EN2.
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*/
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buses_supported = BUS_FWH;
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internal_buses_supported = BUS_FWH;
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return enable_flash_ich(dev, name, 0x4e);
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}
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@ -412,9 +412,9 @@ idsel_garbage_out:
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msg_pdbg("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh);
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/* If we're called by enable_flash_ich_dc_spi, it will override
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* buses_supported anyway.
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* internal_buses_supported anyway.
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*/
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buses_supported = BUS_FWH;
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internal_buses_supported = BUS_FWH;
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return enable_flash_ich(dev, name, 0xdc);
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}
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@ -434,7 +434,7 @@ static int enable_flash_poulsbo(struct pci_dev *dev, const char *name)
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if (new != old)
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rpci_write_byte(dev, 0xd9, new);
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buses_supported = BUS_FWH;
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internal_buses_supported = BUS_FWH;
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return 0;
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}
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@ -468,12 +468,11 @@ static int enable_flash_tunnelcreek(struct pci_dev *dev, const char *name)
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bnt = mmio_readl(rcrb + 0x3410);
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if (bnt & 0x02) {
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/* If strapped to LPC, no SPI initialization is required */
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buses_supported = BUS_FWH;
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internal_buses_supported = BUS_FWH;
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return 0;
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}
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/* This adds BUS_SPI */
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buses_supported = BUS_SPI;
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if (ich_init_spi(dev, tmp, rcrb, 7) != 0) {
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if (!ret)
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ret = ERROR_NONFATAL;
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@ -556,7 +555,7 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
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* time. At least not with our current code. So we prevent searching
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* on ICH7 when the southbridge is strapped to LPC
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*/
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buses_supported = BUS_FWH;
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internal_buses_supported = BUS_FWH;
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if (ich_generation == CHIPSET_ICH7) {
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if (bbs == 0x03) {
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/* If strapped to LPC, no further SPI initialization is
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@ -564,7 +563,7 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
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return ret;
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} else {
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/* Disable LPC/FWH if strapped to PCI or SPI */
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buses_supported = 0;
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internal_buses_supported = BUS_NONE;
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}
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}
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@ -669,7 +668,7 @@ static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
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#define CS5530_ENABLE_SA2320 (1 << 2)
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#define CS5530_ENABLE_SA20 (1 << 6)
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buses_supported = BUS_PARALLEL;
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internal_buses_supported = BUS_PARALLEL;
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/* Decode 0x000E0000-0x000FFFFF (128 kB), not just 64 kB, and
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* decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 kB.
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* FIXME: Should we really touch the low mapping below 1 MB? Flashrom
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@ -822,7 +821,7 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name)
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(prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
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}
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buses_supported = BUS_LPC | BUS_FWH;
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internal_buses_supported = BUS_LPC | BUS_FWH;
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ret = sb600_probe_spi(dev);
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@ -916,7 +915,7 @@ static int enable_flash_osb4(struct pci_dev *dev, const char *name)
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{
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uint8_t tmp;
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buses_supported = BUS_PARALLEL;
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internal_buses_supported = BUS_PARALLEL;
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tmp = INB(0xc06);
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tmp |= 0x1;
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@ -1016,7 +1015,7 @@ static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name)
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switch ((val >> 5) & 0x3) {
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case 0x0:
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ret = enable_flash_mcp55(dev, name);
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buses_supported = BUS_LPC;
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internal_buses_supported = BUS_LPC;
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msg_pdbg("Flash bus type is LPC\n");
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break;
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case 0x2:
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@ -1024,7 +1023,7 @@ static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name)
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/* SPI is added in mcp6x_spi_init if it works.
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* Do we really want to disable LPC in this case?
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*/
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buses_supported = BUS_NONE;
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internal_buses_supported = BUS_NONE;
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msg_pdbg("Flash bus type is SPI\n");
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msg_pinfo("SPI on this chipset is WIP. Please report any "
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"success or failure by mailing us the verbose "
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@ -1032,7 +1031,7 @@ static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name)
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break;
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default:
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/* Should not happen. */
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buses_supported = BUS_NONE;
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internal_buses_supported = BUS_NONE;
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msg_pdbg("Flash bus type is unknown (none)\n");
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msg_pinfo("Something went wrong with bus type detection.\n");
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goto out_msg;
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@ -1325,7 +1324,6 @@ int chipset_flash_enable(void)
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struct pci_dev *dev = NULL;
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int ret = -2; /* Nothing! */
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int i;
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char *s;
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/* Now let's try to find the chipset we have... */
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for (i = 0; chipset_enables[i].vendor_name != NULL; i++) {
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@ -1377,9 +1375,5 @@ int chipset_flash_enable(void)
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}
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}
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s = flashbuses_to_text(buses_supported);
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msg_pinfo("This chipset supports the following protocols: %s.\n", s);
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free(s);
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return ret;
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}
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@ -443,6 +443,10 @@ int main(int argc, char *argv[])
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ret = 1;
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goto out_shutdown;
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}
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tempstr = flashbuses_to_text(buses_supported);
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msg_pdbg("This programmer supports the following protocols: %s.\n",
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tempstr);
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free(tempstr);
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for (i = 0; i < ARRAY_SIZE(flashes); i++) {
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startchip = probe_flash(startchip, &flashes[i], 0);
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17
drkaiser.c
17
drkaiser.c
@ -39,6 +39,17 @@ const struct pcidev_status drkaiser_pcidev[] = {
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static uint8_t *drkaiser_bar;
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static const struct par_programmer par_programmer_drkaiser = {
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.chip_readb = drkaiser_chip_readb,
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.chip_readw = fallback_chip_readw,
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.chip_readl = fallback_chip_readl,
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.chip_readn = fallback_chip_readn,
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.chip_writeb = drkaiser_chip_writeb,
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.chip_writew = fallback_chip_writew,
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.chip_writel = fallback_chip_writel,
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.chip_writen = fallback_chip_writen,
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};
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static int drkaiser_shutdown(void *data)
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{
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physunmap(drkaiser_bar, DRKAISER_MEMMAP_SIZE);
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@ -64,10 +75,12 @@ int drkaiser_init(void)
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drkaiser_bar = physmap("Dr. Kaiser PC-Waechter flash memory",
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addr, DRKAISER_MEMMAP_SIZE);
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buses_supported = BUS_PARALLEL;
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if (register_shutdown(drkaiser_shutdown, NULL))
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return 1;
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max_rom_decode.parallel = 128 * 1024;
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register_par_programmer(&par_programmer_drkaiser, BUS_PARALLEL);
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return 0;
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}
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@ -75,6 +75,19 @@ static const struct spi_programmer spi_programmer_dummyflasher = {
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.write_256 = dummy_spi_write_256,
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};
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static const struct par_programmer par_programmer_dummy = {
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.chip_readb = dummy_chip_readb,
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.chip_readw = dummy_chip_readw,
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.chip_readl = dummy_chip_readl,
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.chip_readn = dummy_chip_readn,
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.chip_writeb = dummy_chip_writeb,
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.chip_writew = dummy_chip_writew,
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.chip_writel = dummy_chip_writel,
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.chip_writen = dummy_chip_writen,
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};
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enum chipbustype dummy_buses_supported = BUS_NONE;
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static int dummy_shutdown(void *data)
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{
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msg_pspew("%s\n", __func__);
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@ -108,24 +121,24 @@ int dummy_init(void)
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/* Convert the parameters to lowercase. */
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tolower_string(bustext);
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buses_supported = BUS_NONE;
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dummy_buses_supported = BUS_NONE;
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if (strstr(bustext, "parallel")) {
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buses_supported |= BUS_PARALLEL;
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dummy_buses_supported |= BUS_PARALLEL;
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msg_pdbg("Enabling support for %s flash.\n", "parallel");
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}
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if (strstr(bustext, "lpc")) {
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buses_supported |= BUS_LPC;
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dummy_buses_supported |= BUS_LPC;
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msg_pdbg("Enabling support for %s flash.\n", "LPC");
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}
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if (strstr(bustext, "fwh")) {
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buses_supported |= BUS_FWH;
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dummy_buses_supported |= BUS_FWH;
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msg_pdbg("Enabling support for %s flash.\n", "FWH");
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}
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if (strstr(bustext, "spi")) {
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register_spi_programmer(&spi_programmer_dummyflasher);
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dummy_buses_supported |= BUS_SPI;
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msg_pdbg("Enabling support for %s flash.\n", "SPI");
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}
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if (buses_supported == BUS_NONE)
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if (dummy_buses_supported == BUS_NONE)
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msg_pdbg("Support for all flash bus types disabled.\n");
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free(bustext);
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@ -226,6 +239,14 @@ dummy_init_out:
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free(flashchip_contents);
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return 1;
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}
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if (dummy_buses_supported & (BUS_PARALLEL | BUS_LPC | BUS_FWH))
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register_par_programmer(&par_programmer_dummy,
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dummy_buses_supported &
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(BUS_PARALLEL | BUS_LPC |
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BUS_FWH));
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if (dummy_buses_supported & BUS_SPI)
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register_spi_programmer(&spi_programmer_dummyflasher);
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return 0;
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}
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168
flashrom.c
168
flashrom.c
@ -68,14 +68,6 @@ const struct programmer_entry programmer_table[] = {
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.init = internal_init,
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.map_flash_region = physmap,
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.unmap_flash_region = physunmap,
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.chip_readb = internal_chip_readb,
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.chip_readw = internal_chip_readw,
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.chip_readl = internal_chip_readl,
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.chip_readn = internal_chip_readn,
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.chip_writeb = internal_chip_writeb,
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.chip_writew = internal_chip_writew,
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.chip_writel = internal_chip_writel,
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.chip_writen = fallback_chip_writen,
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.delay = internal_delay,
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},
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#endif
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@ -86,14 +78,6 @@ const struct programmer_entry programmer_table[] = {
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.init = dummy_init,
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.map_flash_region = dummy_map,
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.unmap_flash_region = dummy_unmap,
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.chip_readb = dummy_chip_readb,
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.chip_readw = dummy_chip_readw,
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.chip_readl = dummy_chip_readl,
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.chip_readn = dummy_chip_readn,
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.chip_writeb = dummy_chip_writeb,
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.chip_writew = dummy_chip_writew,
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.chip_writel = dummy_chip_writel,
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.chip_writen = dummy_chip_writen,
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.delay = internal_delay,
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},
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#endif
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@ -104,14 +88,6 @@ const struct programmer_entry programmer_table[] = {
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.init = nic3com_init,
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.map_flash_region = fallback_map,
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.unmap_flash_region = fallback_unmap,
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.chip_readb = nic3com_chip_readb,
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.chip_readw = fallback_chip_readw,
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.chip_readl = fallback_chip_readl,
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.chip_readn = fallback_chip_readn,
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.chip_writeb = nic3com_chip_writeb,
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.chip_writew = fallback_chip_writew,
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.chip_writel = fallback_chip_writel,
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.chip_writen = fallback_chip_writen,
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.delay = internal_delay,
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},
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#endif
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@ -124,14 +100,6 @@ const struct programmer_entry programmer_table[] = {
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.init = nicrealtek_init,
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.map_flash_region = fallback_map,
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.unmap_flash_region = fallback_unmap,
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.chip_readb = nicrealtek_chip_readb,
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.chip_readw = fallback_chip_readw,
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.chip_readl = fallback_chip_readl,
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.chip_readn = fallback_chip_readn,
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.chip_writeb = nicrealtek_chip_writeb,
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.chip_writew = fallback_chip_writew,
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.chip_writel = fallback_chip_writel,
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.chip_writen = fallback_chip_writen,
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.delay = internal_delay,
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},
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#endif
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@ -142,14 +110,6 @@ const struct programmer_entry programmer_table[] = {
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.init = nicnatsemi_init,
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.map_flash_region = fallback_map,
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.unmap_flash_region = fallback_unmap,
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.chip_readb = nicnatsemi_chip_readb,
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.chip_readw = fallback_chip_readw,
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.chip_readl = fallback_chip_readl,
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.chip_readn = fallback_chip_readn,
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.chip_writeb = nicnatsemi_chip_writeb,
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.chip_writew = fallback_chip_writew,
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.chip_writel = fallback_chip_writel,
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.chip_writen = fallback_chip_writen,
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.delay = internal_delay,
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},
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#endif
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@ -160,14 +120,6 @@ const struct programmer_entry programmer_table[] = {
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.init = gfxnvidia_init,
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.map_flash_region = fallback_map,
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.unmap_flash_region = fallback_unmap,
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.chip_readb = gfxnvidia_chip_readb,
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.chip_readw = fallback_chip_readw,
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.chip_readl = fallback_chip_readl,
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.chip_readn = fallback_chip_readn,
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.chip_writeb = gfxnvidia_chip_writeb,
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.chip_writew = fallback_chip_writew,
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.chip_writel = fallback_chip_writel,
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.chip_writen = fallback_chip_writen,
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.delay = internal_delay,
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},
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#endif
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@ -178,14 +130,6 @@ const struct programmer_entry programmer_table[] = {
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.init = drkaiser_init,
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.map_flash_region = fallback_map,
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.unmap_flash_region = fallback_unmap,
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.chip_readb = drkaiser_chip_readb,
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.chip_readw = fallback_chip_readw,
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.chip_readl = fallback_chip_readl,
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.chip_readn = fallback_chip_readn,
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.chip_writeb = drkaiser_chip_writeb,
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.chip_writew = fallback_chip_writew,
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.chip_writel = fallback_chip_writel,
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.chip_writen = fallback_chip_writen,
|
||||
.delay = internal_delay,
|
||||
},
|
||||
#endif
|
||||
@ -196,14 +140,6 @@ const struct programmer_entry programmer_table[] = {
|
||||
.init = satasii_init,
|
||||
.map_flash_region = fallback_map,
|
||||
.unmap_flash_region = fallback_unmap,
|
||||
.chip_readb = satasii_chip_readb,
|
||||
.chip_readw = fallback_chip_readw,
|
||||
.chip_readl = fallback_chip_readl,
|
||||
.chip_readn = fallback_chip_readn,
|
||||
.chip_writeb = satasii_chip_writeb,
|
||||
.chip_writew = fallback_chip_writew,
|
||||
.chip_writel = fallback_chip_writel,
|
||||
.chip_writen = fallback_chip_writen,
|
||||
.delay = internal_delay,
|
||||
},
|
||||
#endif
|
||||
@ -214,14 +150,6 @@ const struct programmer_entry programmer_table[] = {
|
||||
.init = atahpt_init,
|
||||
.map_flash_region = fallback_map,
|
||||
.unmap_flash_region = fallback_unmap,
|
||||
.chip_readb = atahpt_chip_readb,
|
||||
.chip_readw = fallback_chip_readw,
|
||||
.chip_readl = fallback_chip_readl,
|
||||
.chip_readn = fallback_chip_readn,
|
||||
.chip_writeb = atahpt_chip_writeb,
|
||||
.chip_writew = fallback_chip_writew,
|
||||
.chip_writel = fallback_chip_writel,
|
||||
.chip_writen = fallback_chip_writen,
|
||||
.delay = internal_delay,
|
||||
},
|
||||
#endif
|
||||
@ -232,14 +160,6 @@ const struct programmer_entry programmer_table[] = {
|
||||
.init = ft2232_spi_init,
|
||||
.map_flash_region = fallback_map,
|
||||
.unmap_flash_region = fallback_unmap,
|
||||
.chip_readb = noop_chip_readb,
|
||||
.chip_readw = fallback_chip_readw,
|
||||
.chip_readl = fallback_chip_readl,
|
||||
.chip_readn = fallback_chip_readn,
|
||||
.chip_writeb = noop_chip_writeb,
|
||||
.chip_writew = fallback_chip_writew,
|
||||
.chip_writel = fallback_chip_writel,
|
||||
.chip_writen = fallback_chip_writen,
|
||||
.delay = internal_delay,
|
||||
},
|
||||
#endif
|
||||
@ -250,14 +170,6 @@ const struct programmer_entry programmer_table[] = {
|
||||
.init = serprog_init,
|
||||
.map_flash_region = fallback_map,
|
||||
.unmap_flash_region = fallback_unmap,
|
||||
.chip_readb = serprog_chip_readb,
|
||||
.chip_readw = fallback_chip_readw,
|
||||
.chip_readl = fallback_chip_readl,
|
||||
.chip_readn = serprog_chip_readn,
|
||||
.chip_writeb = serprog_chip_writeb,
|
||||
.chip_writew = fallback_chip_writew,
|
||||
.chip_writel = fallback_chip_writel,
|
||||
.chip_writen = fallback_chip_writen,
|
||||
.delay = serprog_delay,
|
||||
},
|
||||
#endif
|
||||
@ -268,14 +180,6 @@ const struct programmer_entry programmer_table[] = {
|
||||
.init = buspirate_spi_init,
|
||||
.map_flash_region = fallback_map,
|
||||
.unmap_flash_region = fallback_unmap,
|
||||
.chip_readb = noop_chip_readb,
|
||||
.chip_readw = fallback_chip_readw,
|
||||
.chip_readl = fallback_chip_readl,
|
||||
.chip_readn = fallback_chip_readn,
|
||||
.chip_writeb = noop_chip_writeb,
|
||||
.chip_writew = fallback_chip_writew,
|
||||
.chip_writel = fallback_chip_writel,
|
||||
.chip_writen = fallback_chip_writen,
|
||||
.delay = internal_delay,
|
||||
},
|
||||
#endif
|
||||
@ -286,14 +190,6 @@ const struct programmer_entry programmer_table[] = {
|
||||
.init = dediprog_init,
|
||||
.map_flash_region = fallback_map,
|
||||
.unmap_flash_region = fallback_unmap,
|
||||
.chip_readb = noop_chip_readb,
|
||||
.chip_readw = fallback_chip_readw,
|
||||
.chip_readl = fallback_chip_readl,
|
||||
.chip_readn = fallback_chip_readn,
|
||||
.chip_writeb = noop_chip_writeb,
|
||||
.chip_writew = fallback_chip_writew,
|
||||
.chip_writel = fallback_chip_writel,
|
||||
.chip_writen = fallback_chip_writen,
|
||||
.delay = internal_delay,
|
||||
},
|
||||
#endif
|
||||
@ -304,14 +200,6 @@ const struct programmer_entry programmer_table[] = {
|
||||
.init = rayer_spi_init,
|
||||
.map_flash_region = fallback_map,
|
||||
.unmap_flash_region = fallback_unmap,
|
||||
.chip_readb = noop_chip_readb,
|
||||
.chip_readw = fallback_chip_readw,
|
||||
.chip_readl = fallback_chip_readl,
|
||||
.chip_readn = fallback_chip_readn,
|
||||
.chip_writeb = noop_chip_writeb,
|
||||
.chip_writew = fallback_chip_writew,
|
||||
.chip_writel = fallback_chip_writel,
|
||||
.chip_writen = fallback_chip_writen,
|
||||
.delay = internal_delay,
|
||||
},
|
||||
#endif
|
||||
@ -322,14 +210,6 @@ const struct programmer_entry programmer_table[] = {
|
||||
.init = nicintel_init,
|
||||
.map_flash_region = fallback_map,
|
||||
.unmap_flash_region = fallback_unmap,
|
||||
.chip_readb = nicintel_chip_readb,
|
||||
.chip_readw = fallback_chip_readw,
|
||||
.chip_readl = fallback_chip_readl,
|
||||
.chip_readn = fallback_chip_readn,
|
||||
.chip_writeb = nicintel_chip_writeb,
|
||||
.chip_writew = fallback_chip_writew,
|
||||
.chip_writel = fallback_chip_writel,
|
||||
.chip_writen = fallback_chip_writen,
|
||||
.delay = internal_delay,
|
||||
},
|
||||
#endif
|
||||
@ -340,14 +220,6 @@ const struct programmer_entry programmer_table[] = {
|
||||
.init = nicintel_spi_init,
|
||||
.map_flash_region = fallback_map,
|
||||
.unmap_flash_region = fallback_unmap,
|
||||
.chip_readb = noop_chip_readb,
|
||||
.chip_readw = fallback_chip_readw,
|
||||
.chip_readl = fallback_chip_readl,
|
||||
.chip_readn = fallback_chip_readn,
|
||||
.chip_writeb = noop_chip_writeb,
|
||||
.chip_writew = fallback_chip_writew,
|
||||
.chip_writel = fallback_chip_writel,
|
||||
.chip_writen = fallback_chip_writen,
|
||||
.delay = internal_delay,
|
||||
},
|
||||
#endif
|
||||
@ -358,14 +230,6 @@ const struct programmer_entry programmer_table[] = {
|
||||
.init = ogp_spi_init,
|
||||
.map_flash_region = fallback_map,
|
||||
.unmap_flash_region = fallback_unmap,
|
||||
.chip_readb = noop_chip_readb,
|
||||
.chip_readw = fallback_chip_readw,
|
||||
.chip_readl = fallback_chip_readl,
|
||||
.chip_readn = fallback_chip_readn,
|
||||
.chip_writeb = noop_chip_writeb,
|
||||
.chip_writew = fallback_chip_writew,
|
||||
.chip_writel = fallback_chip_writel,
|
||||
.chip_writen = fallback_chip_writen,
|
||||
.delay = internal_delay,
|
||||
},
|
||||
#endif
|
||||
@ -376,14 +240,6 @@ const struct programmer_entry programmer_table[] = {
|
||||
.init = satamv_init,
|
||||
.map_flash_region = fallback_map,
|
||||
.unmap_flash_region = fallback_unmap,
|
||||
.chip_readb = satamv_chip_readb,
|
||||
.chip_readw = fallback_chip_readw,
|
||||
.chip_readl = fallback_chip_readl,
|
||||
.chip_readn = fallback_chip_readn,
|
||||
.chip_writeb = satamv_chip_writeb,
|
||||
.chip_writew = fallback_chip_writew,
|
||||
.chip_writel = fallback_chip_writel,
|
||||
.chip_writen = fallback_chip_writen,
|
||||
.delay = internal_delay,
|
||||
},
|
||||
#endif
|
||||
@ -394,14 +250,6 @@ const struct programmer_entry programmer_table[] = {
|
||||
.init = linux_spi_init,
|
||||
.map_flash_region = fallback_map,
|
||||
.unmap_flash_region = fallback_unmap,
|
||||
.chip_readb = noop_chip_readb,
|
||||
.chip_readw = fallback_chip_readw,
|
||||
.chip_readl = fallback_chip_readl,
|
||||
.chip_readn = fallback_chip_readn,
|
||||
.chip_writeb = noop_chip_writeb,
|
||||
.chip_writew = fallback_chip_writew,
|
||||
.chip_writel = fallback_chip_writel,
|
||||
.chip_writen = fallback_chip_writen,
|
||||
.delay = internal_delay,
|
||||
},
|
||||
#endif
|
||||
@ -513,42 +361,42 @@ void programmer_unmap_flash_region(void *virt_addr, size_t len)
|
||||
|
||||
void chip_writeb(uint8_t val, chipaddr addr)
|
||||
{
|
||||
programmer_table[programmer].chip_writeb(val, addr);
|
||||
par_programmer->chip_writeb(val, addr);
|
||||
}
|
||||
|
||||
void chip_writew(uint16_t val, chipaddr addr)
|
||||
{
|
||||
programmer_table[programmer].chip_writew(val, addr);
|
||||
par_programmer->chip_writew(val, addr);
|
||||
}
|
||||
|
||||
void chip_writel(uint32_t val, chipaddr addr)
|
||||
{
|
||||
programmer_table[programmer].chip_writel(val, addr);
|
||||
par_programmer->chip_writel(val, addr);
|
||||
}
|
||||
|
||||
void chip_writen(uint8_t *buf, chipaddr addr, size_t len)
|
||||
{
|
||||
programmer_table[programmer].chip_writen(buf, addr, len);
|
||||
par_programmer->chip_writen(buf, addr, len);
|
||||
}
|
||||
|
||||
uint8_t chip_readb(const chipaddr addr)
|
||||
{
|
||||
return programmer_table[programmer].chip_readb(addr);
|
||||
return par_programmer->chip_readb(addr);
|
||||
}
|
||||
|
||||
uint16_t chip_readw(const chipaddr addr)
|
||||
{
|
||||
return programmer_table[programmer].chip_readw(addr);
|
||||
return par_programmer->chip_readw(addr);
|
||||
}
|
||||
|
||||
uint32_t chip_readl(const chipaddr addr)
|
||||
{
|
||||
return programmer_table[programmer].chip_readl(addr);
|
||||
return par_programmer->chip_readl(addr);
|
||||
}
|
||||
|
||||
void chip_readn(uint8_t *buf, chipaddr addr, size_t len)
|
||||
{
|
||||
programmer_table[programmer].chip_readn(buf, addr, len);
|
||||
par_programmer->chip_readn(buf, addr, len);
|
||||
}
|
||||
|
||||
void programmer_delay(int usecs)
|
||||
|
||||
14
gfxnvidia.c
14
gfxnvidia.c
@ -61,6 +61,17 @@ const struct pcidev_status gfx_nvidia[] = {
|
||||
{},
|
||||
};
|
||||
|
||||
static const struct par_programmer par_programmer_gfxnvidia = {
|
||||
.chip_readb = gfxnvidia_chip_readb,
|
||||
.chip_readw = fallback_chip_readw,
|
||||
.chip_readl = fallback_chip_readl,
|
||||
.chip_readn = fallback_chip_readn,
|
||||
.chip_writeb = gfxnvidia_chip_writeb,
|
||||
.chip_writew = fallback_chip_writew,
|
||||
.chip_writel = fallback_chip_writel,
|
||||
.chip_writen = fallback_chip_writen,
|
||||
};
|
||||
|
||||
static int gfxnvidia_shutdown(void *data)
|
||||
{
|
||||
physunmap(nvidia_bar, GFXNVIDIA_MEMMAP_SIZE);
|
||||
@ -94,10 +105,9 @@ int gfxnvidia_init(void)
|
||||
reg32 &= ~(1 << 0);
|
||||
rpci_write_long(pcidev_dev, 0x50, reg32);
|
||||
|
||||
buses_supported = BUS_PARALLEL;
|
||||
|
||||
/* Write/erase doesn't work. */
|
||||
programmer_may_write = 0;
|
||||
register_par_programmer(&par_programmer_gfxnvidia, BUS_PARALLEL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
2
ichspi.c
2
ichspi.c
@ -1796,7 +1796,7 @@ int via_init_spi(struct pci_dev *dev)
|
||||
ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70);
|
||||
|
||||
/* Not sure if it speaks all these bus protocols. */
|
||||
buses_supported = BUS_LPC | BUS_FWH;
|
||||
internal_buses_supported = BUS_LPC | BUS_FWH;
|
||||
ich_generation = CHIPSET_ICH7;
|
||||
register_spi_programmer(&spi_programmer_via);
|
||||
|
||||
|
||||
19
internal.c
19
internal.c
@ -127,6 +127,19 @@ int register_superio(struct superio s)
|
||||
int is_laptop = 0;
|
||||
int laptop_ok = 0;
|
||||
|
||||
static const struct par_programmer par_programmer_internal = {
|
||||
.chip_readb = internal_chip_readb,
|
||||
.chip_readw = internal_chip_readw,
|
||||
.chip_readl = internal_chip_readl,
|
||||
.chip_readn = internal_chip_readn,
|
||||
.chip_writeb = internal_chip_writeb,
|
||||
.chip_writew = internal_chip_writew,
|
||||
.chip_writel = internal_chip_writel,
|
||||
.chip_writen = fallback_chip_writen,
|
||||
};
|
||||
|
||||
enum chipbustype internal_buses_supported = BUS_NONE;
|
||||
|
||||
static int internal_shutdown(void *data)
|
||||
{
|
||||
release_io_perms();
|
||||
@ -191,9 +204,10 @@ int internal_init(void)
|
||||
return 1;
|
||||
|
||||
/* Default to Parallel/LPC/FWH flash devices. If a known host controller
|
||||
* is found, the init routine sets the buses_supported bitfield.
|
||||
* is found, the host controller init routine sets the
|
||||
* internal_buses_supported bitfield.
|
||||
*/
|
||||
buses_supported = BUS_NONSPI;
|
||||
internal_buses_supported = BUS_NONSPI;
|
||||
|
||||
/* Initialize PCI access for flash enables */
|
||||
pacc = pci_alloc(); /* Get the pci_access structure */
|
||||
@ -287,6 +301,7 @@ int internal_init(void)
|
||||
* Besides that, we don't check the board enable return code either.
|
||||
*/
|
||||
#if defined(__i386__) || defined(__x86_64__) || defined (__mips)
|
||||
register_par_programmer(&par_programmer_internal, internal_buses_supported);
|
||||
return 0;
|
||||
#else
|
||||
msg_perr("Your platform is not supported yet for the internal "
|
||||
|
||||
26
it85spi.c
26
it85spi.c
@ -257,8 +257,10 @@ static int it85xx_spi_common_init(struct superio s)
|
||||
INDIRECT_A3(shm_io_base, (base >> 24));
|
||||
#endif
|
||||
#ifdef LPC_MEMORY
|
||||
base = (chipaddr)programmer_map_flash_region("it85 communication",
|
||||
0xFFFFF000, 0x1000);
|
||||
/* FIXME: We should block accessing that region for anything else.
|
||||
* Major TODO here, and it will be a lot of work.
|
||||
*/
|
||||
base = (chipaddr)physmap("it85 communication", 0xFFFFF000, 0x1000);
|
||||
msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__,
|
||||
(unsigned int)base);
|
||||
ce_high = (unsigned char *)(base + 0xE00); /* 0xFFFFFE00 */
|
||||
@ -285,18 +287,26 @@ int it85xx_spi_init(struct superio s)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (!(buses_supported & BUS_FWH)) {
|
||||
if (!(internal_buses_supported & BUS_FWH)) {
|
||||
msg_pdbg("%s():%d buses not support FWH\n", __func__, __LINE__);
|
||||
return 1;
|
||||
}
|
||||
ret = it85xx_spi_common_init(s);
|
||||
msg_pdbg("FWH: %s():%d ret=%d\n", __func__, __LINE__, ret);
|
||||
if (!ret) {
|
||||
msg_pdbg("%s():%d buses_supported=0x%x\n", __func__, __LINE__,
|
||||
buses_supported);
|
||||
if (buses_supported & BUS_FWH)
|
||||
msg_pdbg("Overriding chipset SPI with IT85 FWH|SPI.\n");
|
||||
/* Really leave FWH enabled? */
|
||||
msg_pdbg("%s: internal_buses_supported=0x%x\n", __func__,
|
||||
internal_buses_supported);
|
||||
/* Check for FWH because IT85 listens to FWH cycles.
|
||||
* FIXME: The big question is whether FWH cycles are necessary
|
||||
* for communication even if LPC_IO is defined.
|
||||
*/
|
||||
if (internal_buses_supported & BUS_FWH)
|
||||
msg_pdbg("Registering IT85 SPI.\n");
|
||||
/* FIXME: Really leave FWH enabled? We can't use this region
|
||||
* anymore since accessing it would mess up IT85 communication.
|
||||
* If we decide to disable FWH for this region, we should print
|
||||
* a debug message about it.
|
||||
*/
|
||||
/* Set this as SPI controller. */
|
||||
register_spi_programmer(&spi_programmer_it85xx);
|
||||
}
|
||||
|
||||
@ -192,7 +192,7 @@ static uint16_t it87spi_probe(uint16_t port)
|
||||
free(portpos);
|
||||
exit_conf_mode_ite(port);
|
||||
it8716f_flashport = flashport;
|
||||
if (buses_supported & BUS_SPI)
|
||||
if (internal_buses_supported & BUS_SPI)
|
||||
msg_pdbg("Overriding chipset SPI with IT87 SPI.\n");
|
||||
/* FIXME: Add the SPI bus or replace the other buses with it? */
|
||||
register_spi_programmer(&spi_programmer_it87xx);
|
||||
|
||||
18
nic3com.c
18
nic3com.c
@ -55,6 +55,17 @@ const struct pcidev_status nics_3com[] = {
|
||||
{},
|
||||
};
|
||||
|
||||
static const struct par_programmer par_programmer_nic3com = {
|
||||
.chip_readb = nic3com_chip_readb,
|
||||
.chip_readw = fallback_chip_readw,
|
||||
.chip_readl = fallback_chip_readl,
|
||||
.chip_readn = fallback_chip_readn,
|
||||
.chip_writeb = nic3com_chip_writeb,
|
||||
.chip_writew = fallback_chip_writew,
|
||||
.chip_writel = fallback_chip_writel,
|
||||
.chip_writen = fallback_chip_writen,
|
||||
};
|
||||
|
||||
static int nic3com_shutdown(void *data)
|
||||
{
|
||||
/* 3COM 3C90xB cards need a special fixup. */
|
||||
@ -96,11 +107,12 @@ int nic3com_init(void)
|
||||
*/
|
||||
OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS);
|
||||
|
||||
buses_supported = BUS_PARALLEL;
|
||||
max_rom_decode.parallel = 128 * 1024;
|
||||
|
||||
if (register_shutdown(nic3com_shutdown, NULL))
|
||||
return 1;
|
||||
|
||||
max_rom_decode.parallel = 128 * 1024;
|
||||
register_par_programmer(&par_programmer_nic3com, BUS_PARALLEL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
14
nicintel.c
14
nicintel.c
@ -43,6 +43,17 @@ const struct pcidev_status nics_intel[] = {
|
||||
|
||||
#define CSR_FCR 0x0c
|
||||
|
||||
static const struct par_programmer par_programmer_nicintel = {
|
||||
.chip_readb = nicintel_chip_readb,
|
||||
.chip_readw = fallback_chip_readw,
|
||||
.chip_readl = fallback_chip_readl,
|
||||
.chip_readn = fallback_chip_readn,
|
||||
.chip_writeb = nicintel_chip_writeb,
|
||||
.chip_writew = fallback_chip_writew,
|
||||
.chip_writel = fallback_chip_writel,
|
||||
.chip_writen = fallback_chip_writen,
|
||||
};
|
||||
|
||||
static int nicintel_shutdown(void *data)
|
||||
{
|
||||
physunmap(nicintel_control_bar, NICINTEL_CONTROL_MEMMAP_SIZE);
|
||||
@ -93,9 +104,8 @@ int nicintel_init(void)
|
||||
*/
|
||||
pci_rmmio_writew(0x0001, nicintel_control_bar + CSR_FCR);
|
||||
|
||||
buses_supported = BUS_PARALLEL;
|
||||
|
||||
max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE;
|
||||
register_par_programmer(&par_programmer_nicintel, BUS_PARALLEL);
|
||||
|
||||
return 0;
|
||||
|
||||
|
||||
17
nicnatsemi.c
17
nicnatsemi.c
@ -35,6 +35,17 @@ const struct pcidev_status nics_natsemi[] = {
|
||||
{},
|
||||
};
|
||||
|
||||
static const struct par_programmer par_programmer_nicnatsemi = {
|
||||
.chip_readb = nicnatsemi_chip_readb,
|
||||
.chip_readw = fallback_chip_readw,
|
||||
.chip_readl = fallback_chip_readl,
|
||||
.chip_readn = fallback_chip_readn,
|
||||
.chip_writeb = nicnatsemi_chip_writeb,
|
||||
.chip_writew = fallback_chip_writew,
|
||||
.chip_writel = fallback_chip_writel,
|
||||
.chip_writen = fallback_chip_writen,
|
||||
};
|
||||
|
||||
static int nicnatsemi_shutdown(void *data)
|
||||
{
|
||||
pci_cleanup(pacc);
|
||||
@ -48,7 +59,8 @@ int nicnatsemi_init(void)
|
||||
|
||||
io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_natsemi);
|
||||
|
||||
buses_supported = BUS_PARALLEL;
|
||||
if (register_shutdown(nicnatsemi_shutdown, NULL))
|
||||
return 1;
|
||||
|
||||
/* The datasheet shows address lines MA0-MA16 in one place and MA0-MA15
|
||||
* in another. My NIC has MA16 connected to A16 on the boot ROM socket
|
||||
@ -57,9 +69,8 @@ int nicnatsemi_init(void)
|
||||
* functions below wants to be 0x0000FFFF.
|
||||
*/
|
||||
max_rom_decode.parallel = 131072;
|
||||
register_par_programmer(&par_programmer_nicnatsemi, BUS_PARALLEL);
|
||||
|
||||
if (register_shutdown(nicnatsemi_shutdown, NULL))
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
16
nicrealtek.c
16
nicrealtek.c
@ -36,6 +36,17 @@ const struct pcidev_status nics_realtek[] = {
|
||||
{},
|
||||
};
|
||||
|
||||
static const struct par_programmer par_programmer_nicrealtek = {
|
||||
.chip_readb = nicrealtek_chip_readb,
|
||||
.chip_readw = fallback_chip_readw,
|
||||
.chip_readl = fallback_chip_readl,
|
||||
.chip_readn = fallback_chip_readn,
|
||||
.chip_writeb = nicrealtek_chip_writeb,
|
||||
.chip_writew = fallback_chip_writew,
|
||||
.chip_writel = fallback_chip_writel,
|
||||
.chip_writen = fallback_chip_writen,
|
||||
};
|
||||
|
||||
static int nicrealtek_shutdown(void *data)
|
||||
{
|
||||
/* FIXME: We forgot to disable software access again. */
|
||||
@ -50,10 +61,11 @@ int nicrealtek_init(void)
|
||||
|
||||
io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_realtek);
|
||||
|
||||
buses_supported = BUS_PARALLEL;
|
||||
|
||||
if (register_shutdown(nicrealtek_shutdown, NULL))
|
||||
return 1;
|
||||
|
||||
register_par_programmer(&par_programmer_nicrealtek, BUS_PARALLEL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
20
programmer.c
20
programmer.c
@ -19,6 +19,20 @@
|
||||
*/
|
||||
|
||||
#include "flash.h"
|
||||
#include "programmer.h"
|
||||
|
||||
static const struct par_programmer par_programmer_none = {
|
||||
.chip_readb = noop_chip_readb,
|
||||
.chip_readw = fallback_chip_readw,
|
||||
.chip_readl = fallback_chip_readl,
|
||||
.chip_readn = fallback_chip_readn,
|
||||
.chip_writeb = noop_chip_writeb,
|
||||
.chip_writew = fallback_chip_writew,
|
||||
.chip_writel = fallback_chip_writel,
|
||||
.chip_writen = fallback_chip_writen,
|
||||
};
|
||||
|
||||
const struct par_programmer *par_programmer = &par_programmer_none;
|
||||
|
||||
/* No-op shutdown() for programmers which don't need special handling */
|
||||
int noop_shutdown(void)
|
||||
@ -96,3 +110,9 @@ void fallback_chip_readn(uint8_t *buf, chipaddr addr, size_t len)
|
||||
buf[i] = chip_readb(addr + i);
|
||||
return;
|
||||
}
|
||||
|
||||
void register_par_programmer(const struct par_programmer *pgm, const enum chipbustype buses)
|
||||
{
|
||||
par_programmer = pgm;
|
||||
buses_supported |= buses;
|
||||
}
|
||||
|
||||
25
programmer.h
25
programmer.h
@ -97,14 +97,6 @@ struct programmer_entry {
|
||||
size_t len);
|
||||
void (*unmap_flash_region) (void *virt_addr, size_t len);
|
||||
|
||||
void (*chip_writeb) (uint8_t val, chipaddr addr);
|
||||
void (*chip_writew) (uint16_t val, chipaddr addr);
|
||||
void (*chip_writel) (uint32_t val, chipaddr addr);
|
||||
void (*chip_writen) (uint8_t *buf, chipaddr addr, size_t len);
|
||||
uint8_t (*chip_readb) (const chipaddr addr);
|
||||
uint16_t (*chip_readw) (const chipaddr addr);
|
||||
uint32_t (*chip_readl) (const chipaddr addr);
|
||||
void (*chip_readn) (uint8_t *buf, const chipaddr addr, size_t len);
|
||||
void (*delay) (int usecs);
|
||||
};
|
||||
|
||||
@ -306,6 +298,7 @@ extern int force_boardenable;
|
||||
extern int force_boardmismatch;
|
||||
void probe_superio(void);
|
||||
int register_superio(struct superio s);
|
||||
extern enum chipbustype internal_buses_supported;
|
||||
int internal_init(void);
|
||||
void internal_chip_writeb(uint8_t val, chipaddr addr);
|
||||
void internal_chip_writew(uint16_t val, chipaddr addr);
|
||||
@ -360,6 +353,18 @@ void fallback_chip_writen(uint8_t *buf, chipaddr addr, size_t len);
|
||||
uint16_t fallback_chip_readw(const chipaddr addr);
|
||||
uint32_t fallback_chip_readl(const chipaddr addr);
|
||||
void fallback_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);
|
||||
struct par_programmer {
|
||||
void (*chip_writeb) (uint8_t val, chipaddr addr);
|
||||
void (*chip_writew) (uint16_t val, chipaddr addr);
|
||||
void (*chip_writel) (uint32_t val, chipaddr addr);
|
||||
void (*chip_writen) (uint8_t *buf, chipaddr addr, size_t len);
|
||||
uint8_t (*chip_readb) (const chipaddr addr);
|
||||
uint16_t (*chip_readw) (const chipaddr addr);
|
||||
uint32_t (*chip_readl) (const chipaddr addr);
|
||||
void (*chip_readn) (uint8_t *buf, const chipaddr addr, size_t len);
|
||||
};
|
||||
extern const struct par_programmer *par_programmer;
|
||||
void register_par_programmer(const struct par_programmer *pgm, const enum chipbustype buses);
|
||||
|
||||
/* dummyflasher.c */
|
||||
#if CONFIG_DUMMY == 1
|
||||
@ -634,10 +639,6 @@ void serprog_chip_writeb(uint8_t val, chipaddr addr);
|
||||
uint8_t serprog_chip_readb(const chipaddr addr);
|
||||
void serprog_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);
|
||||
void serprog_delay(int usecs);
|
||||
int serprog_spi_send_command(unsigned int writecnt, unsigned int readcnt,
|
||||
const unsigned char *writearr,
|
||||
unsigned char *readarr);
|
||||
int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);
|
||||
#endif
|
||||
|
||||
/* serial.c */
|
||||
|
||||
14
satamv.c
14
satamv.c
@ -41,6 +41,17 @@ const struct pcidev_status satas_mv[] = {
|
||||
#define PCI_BAR2_CONTROL 0x00c08
|
||||
#define GPIO_PORT_CONTROL 0x104f0
|
||||
|
||||
static const struct par_programmer par_programmer_satamv = {
|
||||
.chip_readb = satamv_chip_readb,
|
||||
.chip_readw = fallback_chip_readw,
|
||||
.chip_readl = fallback_chip_readl,
|
||||
.chip_readn = fallback_chip_readn,
|
||||
.chip_writeb = satamv_chip_writeb,
|
||||
.chip_writew = fallback_chip_writew,
|
||||
.chip_writel = fallback_chip_writel,
|
||||
.chip_writen = fallback_chip_writen,
|
||||
};
|
||||
|
||||
static int satamv_shutdown(void *data)
|
||||
{
|
||||
physunmap(mv_bar, 0x20000);
|
||||
@ -137,11 +148,10 @@ int satamv_init(void)
|
||||
mv_iobar = tmp & 0xffff;
|
||||
msg_pspew("Activating I/O BAR at 0x%04x\n", mv_iobar);
|
||||
|
||||
buses_supported = BUS_PARALLEL;
|
||||
|
||||
/* 512 kByte with two 8-bit latches, and
|
||||
* 4 MByte with additional 3-bit latch. */
|
||||
max_rom_decode.parallel = 4 * 1024 * 1024;
|
||||
register_par_programmer(&par_programmer_satamv, BUS_PARALLEL);
|
||||
|
||||
return 0;
|
||||
|
||||
|
||||
16
satasii.c
16
satasii.c
@ -42,6 +42,17 @@ const struct pcidev_status satas_sii[] = {
|
||||
{},
|
||||
};
|
||||
|
||||
static const struct par_programmer par_programmer_satasii = {
|
||||
.chip_readb = satasii_chip_readb,
|
||||
.chip_readw = fallback_chip_readw,
|
||||
.chip_readl = fallback_chip_readl,
|
||||
.chip_readn = fallback_chip_readn,
|
||||
.chip_writeb = satasii_chip_writeb,
|
||||
.chip_writew = fallback_chip_writew,
|
||||
.chip_writel = fallback_chip_writel,
|
||||
.chip_writen = fallback_chip_writen,
|
||||
};
|
||||
|
||||
static int satasii_shutdown(void *data)
|
||||
{
|
||||
physunmap(sii_bar, SATASII_MEMMAP_SIZE);
|
||||
@ -76,10 +87,11 @@ int satasii_init(void)
|
||||
if ((id != 0x0680) && (!(pci_mmio_readl(sii_bar) & (1 << 26))))
|
||||
msg_pinfo("Warning: Flash seems unconnected.\n");
|
||||
|
||||
buses_supported = BUS_PARALLEL;
|
||||
|
||||
if (register_shutdown(satasii_shutdown, NULL))
|
||||
return 1;
|
||||
|
||||
register_par_programmer(&par_programmer_satasii, BUS_PARALLEL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
66
serprog.c
66
serprog.c
@ -299,6 +299,11 @@ static int sp_stream_buffer_op(uint8_t cmd, uint32_t parmlen, uint8_t * parms)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int serprog_spi_send_command(unsigned int writecnt, unsigned int readcnt,
|
||||
const unsigned char *writearr,
|
||||
unsigned char *readarr);
|
||||
static int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start,
|
||||
int len);
|
||||
static struct spi_programmer spi_programmer_serprog = {
|
||||
.type = SPI_CONTROLLER_SERPROG,
|
||||
.max_data_read = MAX_DATA_READ_UNLIMITED,
|
||||
@ -309,6 +314,19 @@ static struct spi_programmer spi_programmer_serprog = {
|
||||
.write_256 = default_spi_write_256,
|
||||
};
|
||||
|
||||
static const struct par_programmer par_programmer_serprog = {
|
||||
.chip_readb = serprog_chip_readb,
|
||||
.chip_readw = fallback_chip_readw,
|
||||
.chip_readl = fallback_chip_readl,
|
||||
.chip_readn = serprog_chip_readn,
|
||||
.chip_writeb = serprog_chip_writeb,
|
||||
.chip_writew = fallback_chip_writew,
|
||||
.chip_writel = fallback_chip_writel,
|
||||
.chip_writen = fallback_chip_writen,
|
||||
};
|
||||
|
||||
static enum chipbustype serprog_buses_supported = BUS_NONE;
|
||||
|
||||
int serprog_init(void)
|
||||
{
|
||||
uint16_t iface;
|
||||
@ -400,41 +418,45 @@ int serprog_init(void)
|
||||
|
||||
if (sp_docommand(S_CMD_Q_IFACE, 0, NULL, 2, &iface)) {
|
||||
msg_perr("Error: NAK to query interface version\n");
|
||||
exit(1);
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (iface != 1) {
|
||||
msg_perr("Error: Unknown interface version: %d\n", iface);
|
||||
exit(1);
|
||||
return 1;
|
||||
}
|
||||
|
||||
msg_pdbg(MSGHEADER "Interface version ok.\n");
|
||||
|
||||
if (sp_docommand(S_CMD_Q_CMDMAP, 0, NULL, 32, sp_cmdmap)) {
|
||||
msg_perr("Error: query command map not supported\n");
|
||||
exit(1);
|
||||
return 1;
|
||||
}
|
||||
|
||||
sp_check_avail_automatic = 1;
|
||||
|
||||
|
||||
/* FIXME: This assumes that serprog device bustypes are always
|
||||
* identical with flashrom bustype enums and that they all fit
|
||||
* in a single byte.
|
||||
*/
|
||||
if (sp_docommand(S_CMD_Q_BUSTYPE, 0, NULL, 1, &c)) {
|
||||
msg_perr("Warning: NAK to query supported buses\n");
|
||||
c = BUS_NONSPI; /* A reasonable default for now. */
|
||||
}
|
||||
buses_supported = c;
|
||||
serprog_buses_supported = c;
|
||||
|
||||
msg_pdbg(MSGHEADER "Bus support: parallel=%s, LPC=%s, FWH=%s, SPI=%s\n",
|
||||
(c & BUS_PARALLEL) ? "on" : "off",
|
||||
(c & BUS_LPC) ? "on" : "off",
|
||||
(c & BUS_FWH) ? "on" : "off",
|
||||
(c & BUS_SPI) ? "on" : "off");
|
||||
/* Check for the minimum operational set of commands. */
|
||||
if (buses_supported & BUS_SPI) {
|
||||
if (serprog_buses_supported & BUS_SPI) {
|
||||
uint8_t bt = BUS_SPI;
|
||||
if (sp_check_commandavail(S_CMD_O_SPIOP) == 0) {
|
||||
msg_perr("Error: SPI operation not supported while the "
|
||||
"bustype is SPI\n");
|
||||
exit(1);
|
||||
return 1;
|
||||
}
|
||||
/* Success of any of these commands is optional. We don't need
|
||||
the programmer to tell us its limits, but if it doesn't, we
|
||||
@ -461,40 +483,39 @@ int serprog_init(void)
|
||||
spi_programmer_serprog.max_data_read = v;
|
||||
msg_pdbg(MSGHEADER "Maximum read-n length is %d\n", v);
|
||||
}
|
||||
bt = buses_supported;
|
||||
bt = serprog_buses_supported;
|
||||
sp_docommand(S_CMD_S_BUSTYPE, 1, &bt, 0, NULL);
|
||||
register_spi_programmer(&spi_programmer_serprog);
|
||||
}
|
||||
|
||||
if (buses_supported & BUS_NONSPI) {
|
||||
if (serprog_buses_supported & BUS_NONSPI) {
|
||||
if (sp_check_commandavail(S_CMD_O_INIT) == 0) {
|
||||
msg_perr("Error: Initialize operation buffer "
|
||||
"not supported\n");
|
||||
exit(1);
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (sp_check_commandavail(S_CMD_O_DELAY) == 0) {
|
||||
msg_perr("Error: Write to opbuf: "
|
||||
"delay not supported\n");
|
||||
exit(1);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* S_CMD_O_EXEC availability checked later. */
|
||||
|
||||
if (sp_check_commandavail(S_CMD_R_BYTE) == 0) {
|
||||
msg_perr("Error: Single byte read not supported\n");
|
||||
exit(1);
|
||||
return 1;
|
||||
}
|
||||
/* This could be translated to single byte reads (if missing),
|
||||
* but now we don't support that. */
|
||||
if (sp_check_commandavail(S_CMD_R_NBYTES) == 0) {
|
||||
msg_perr("Error: Read n bytes not supported\n");
|
||||
exit(1);
|
||||
return 1;
|
||||
}
|
||||
if (sp_check_commandavail(S_CMD_O_WRITEB) == 0) {
|
||||
msg_perr("Error: Write to opbuf: "
|
||||
"write byte not supported\n");
|
||||
exit(1);
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (sp_docommand(S_CMD_Q_WRNMAXLEN, 0, NULL, 3, rbuf)) {
|
||||
@ -513,7 +534,7 @@ int serprog_init(void)
|
||||
if (!sp_write_n_buf) {
|
||||
msg_perr("Error: cannot allocate memory for "
|
||||
"Write-n buffer\n");
|
||||
exit(1);
|
||||
return 1;
|
||||
}
|
||||
sp_write_n_bytes = 0;
|
||||
}
|
||||
@ -551,12 +572,12 @@ int serprog_init(void)
|
||||
if (sp_check_commandavail(S_CMD_O_EXEC) == 0) {
|
||||
msg_perr("Error: Execute operation buffer not "
|
||||
"supported\n");
|
||||
exit(1);
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (sp_docommand(S_CMD_O_INIT, 0, NULL, 0, NULL)) {
|
||||
msg_perr("Error: NAK to initialize operation buffer\n");
|
||||
exit(1);
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (sp_docommand(S_CMD_Q_OPBUF, 0, NULL, 2,
|
||||
@ -572,6 +593,11 @@ int serprog_init(void)
|
||||
sp_streamed_transmit_ops = 0;
|
||||
sp_streamed_transmit_bytes = 0;
|
||||
sp_opbuf_usage = 0;
|
||||
if (serprog_buses_supported & BUS_SPI)
|
||||
register_spi_programmer(&spi_programmer_serprog);
|
||||
if (serprog_buses_supported & BUS_NONSPI)
|
||||
register_par_programmer(&par_programmer_serprog,
|
||||
serprog_buses_supported & BUS_NONSPI);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -766,7 +792,7 @@ void serprog_delay(int usecs)
|
||||
sp_prev_was_write = 0;
|
||||
}
|
||||
|
||||
int serprog_spi_send_command(unsigned int writecnt, unsigned int readcnt,
|
||||
static int serprog_spi_send_command(unsigned int writecnt, unsigned int readcnt,
|
||||
const unsigned char *writearr,
|
||||
unsigned char *readarr)
|
||||
{
|
||||
@ -796,7 +822,7 @@ int serprog_spi_send_command(unsigned int writecnt, unsigned int readcnt,
|
||||
* the advantage that it is much faster for most chips, but breaks those with
|
||||
* non-contiguous address space (like AT45DB161D). When spi_read_chunked is
|
||||
* fixed this method can be removed. */
|
||||
int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len)
|
||||
static int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len)
|
||||
{
|
||||
int i;
|
||||
int cur_len;
|
||||
|
||||
@ -82,10 +82,10 @@ int wbsio_check_for_spi(void)
|
||||
|
||||
msg_pspew("\nwbsio_spibase = 0x%x\n", wbsio_spibase);
|
||||
|
||||
register_spi_programmer(&spi_programmer_wbsio);
|
||||
msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is "
|
||||
"1024 kB!\n", __func__);
|
||||
max_rom_decode.spi = 1024 * 1024;
|
||||
register_spi_programmer(&spi_programmer_wbsio);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user