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Register Parallel/LPC/FWH programmers the same way SPI programmers are registered

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All programmers are now calling programmer registration functions and
direct manipulations of buses_supported are not needed/possible anymore.

Note: Programmers without parallel/LPC/FWH chip support should not call
register_par_programmer().

Additional fixes:
Set max_rom_decode.parallel for drkaiser.
Remove abuse of programmer_map_flash_region in it85spi.
Annotate several FIXMEs in it85spi.

Corresponding to flashrom svn r1463.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
This commit is contained in:
Carl-Daniel Hailfinger
2011-11-09 23:40:00 +00:00
parent f382e352ac
commit eaacd2d4e7
22 changed files with 293 additions and 252 deletions
Download Patch File Download Diff File Expand all files Collapse all files

34
chipset_enable.c
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@ -213,7 +213,7 @@ static int enable_flash_piix4(struct pci_dev *dev, const char *name)
uint16_t old, new;
uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
buses_supported = BUS_PARALLEL;
internal_buses_supported = BUS_PARALLEL;
old = pci_read_word(dev, xbcs);
@ -303,7 +303,7 @@ static int enable_flash_ich_4e(struct pci_dev *dev, const char *name)
* FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and
* FB_DEC_EN2.
*/
buses_supported = BUS_FWH;
internal_buses_supported = BUS_FWH;
return enable_flash_ich(dev, name, 0x4e);
}
@ -412,9 +412,9 @@ idsel_garbage_out:
msg_pdbg("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh);
/* If we're called by enable_flash_ich_dc_spi, it will override
* buses_supported anyway.
* internal_buses_supported anyway.
*/
buses_supported = BUS_FWH;
internal_buses_supported = BUS_FWH;
return enable_flash_ich(dev, name, 0xdc);
}
@ -434,7 +434,7 @@ static int enable_flash_poulsbo(struct pci_dev *dev, const char *name)
if (new != old)
rpci_write_byte(dev, 0xd9, new);
buses_supported = BUS_FWH;
internal_buses_supported = BUS_FWH;
return 0;
}
@ -468,12 +468,11 @@ static int enable_flash_tunnelcreek(struct pci_dev *dev, const char *name)
bnt = mmio_readl(rcrb + 0x3410);
if (bnt & 0x02) {
/* If strapped to LPC, no SPI initialization is required */
buses_supported = BUS_FWH;
internal_buses_supported = BUS_FWH;
return 0;
}
/* This adds BUS_SPI */
buses_supported = BUS_SPI;
if (ich_init_spi(dev, tmp, rcrb, 7) != 0) {
if (!ret)
ret = ERROR_NONFATAL;
@ -556,7 +555,7 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
* time. At least not with our current code. So we prevent searching
* on ICH7 when the southbridge is strapped to LPC
*/
buses_supported = BUS_FWH;
internal_buses_supported = BUS_FWH;
if (ich_generation == CHIPSET_ICH7) {
if (bbs == 0x03) {
/* If strapped to LPC, no further SPI initialization is
@ -564,7 +563,7 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
return ret;
} else {
/* Disable LPC/FWH if strapped to PCI or SPI */
buses_supported = 0;
internal_buses_supported = BUS_NONE;
}
}
@ -669,7 +668,7 @@ static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
#define CS5530_ENABLE_SA2320 (1 << 2)
#define CS5530_ENABLE_SA20 (1 << 6)
buses_supported = BUS_PARALLEL;
internal_buses_supported = BUS_PARALLEL;
/* Decode 0x000E0000-0x000FFFFF (128 kB), not just 64 kB, and
* decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 kB.
* FIXME: Should we really touch the low mapping below 1 MB? Flashrom
@ -822,7 +821,7 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name)
(prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
}
buses_supported = BUS_LPC | BUS_FWH;
internal_buses_supported = BUS_LPC | BUS_FWH;
ret = sb600_probe_spi(dev);
@ -916,7 +915,7 @@ static int enable_flash_osb4(struct pci_dev *dev, const char *name)
{
uint8_t tmp;
buses_supported = BUS_PARALLEL;
internal_buses_supported = BUS_PARALLEL;
tmp = INB(0xc06);
tmp |= 0x1;
@ -1016,7 +1015,7 @@ static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name)
switch ((val >> 5) & 0x3) {
case 0x0:
ret = enable_flash_mcp55(dev, name);
buses_supported = BUS_LPC;
internal_buses_supported = BUS_LPC;
msg_pdbg("Flash bus type is LPC\n");
break;
case 0x2:
@ -1024,7 +1023,7 @@ static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name)
/* SPI is added in mcp6x_spi_init if it works.
* Do we really want to disable LPC in this case?
*/
buses_supported = BUS_NONE;
internal_buses_supported = BUS_NONE;
msg_pdbg("Flash bus type is SPI\n");
msg_pinfo("SPI on this chipset is WIP. Please report any "
"success or failure by mailing us the verbose "
@ -1032,7 +1031,7 @@ static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name)
break;
default:
/* Should not happen. */
buses_supported = BUS_NONE;
internal_buses_supported = BUS_NONE;
msg_pdbg("Flash bus type is unknown (none)\n");
msg_pinfo("Something went wrong with bus type detection.\n");
goto out_msg;
@ -1325,7 +1324,6 @@ int chipset_flash_enable(void)
struct pci_dev *dev = NULL;
int ret = -2; /* Nothing! */
int i;
char *s;
/* Now let's try to find the chipset we have... */
for (i = 0; chipset_enables[i].vendor_name != NULL; i++) {
@ -1377,9 +1375,5 @@ int chipset_flash_enable(void)
}
}
s = flashbuses_to_text(buses_supported);
msg_pinfo("This chipset supports the following protocols: %s.\n", s);
free(s);
return ret;
}