openwrt/flashrom
1
0
Fork 0
mirror of https://review.coreboot.org/flashrom.git synced 2025-06-30 21:52:36 +02:00
Code Issues Releases Wiki Activity

Register Parallel/LPC/FWH programmers the same way SPI programmers are registered

Browse Source 
All programmers are now calling programmer registration functions and
direct manipulations of buses_supported are not needed/possible anymore.

Note: Programmers without parallel/LPC/FWH chip support should not call
register_par_programmer().

Additional fixes:
Set max_rom_decode.parallel for drkaiser.
Remove abuse of programmer_map_flash_region in it85spi.
Annotate several FIXMEs in it85spi.

Corresponding to flashrom svn r1463.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
This commit is contained in:
Carl-Daniel Hailfinger
2011-11-09 23:40:00 +00:00
parent f382e352ac
commit eaacd2d4e7
22 changed files with 293 additions and 252 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
nicintel.c
View File

@ -43,6 +43,17 @@ const struct pcidev_status nics_intel[] = {
#define CSR_FCR 0x0c
static const struct par_programmer par_programmer_nicintel = {
.chip_readb = nicintel_chip_readb,
.chip_readw = fallback_chip_readw,
.chip_readl = fallback_chip_readl,
.chip_readn = fallback_chip_readn,
.chip_writeb = nicintel_chip_writeb,
.chip_writew = fallback_chip_writew,
.chip_writel = fallback_chip_writel,
.chip_writen = fallback_chip_writen,
};
static int nicintel_shutdown(void *data)
{
physunmap(nicintel_control_bar, NICINTEL_CONTROL_MEMMAP_SIZE);
@ -93,9 +104,8 @@ int nicintel_init(void)
*/
pci_rmmio_writew(0x0001, nicintel_control_bar + CSR_FCR);
buses_supported = BUS_PARALLEL;
max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE;
register_par_programmer(&par_programmer_nicintel, BUS_PARALLEL);
return 0;