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Register Parallel/LPC/FWH programmers the same way SPI programmers are registered

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All programmers are now calling programmer registration functions and
direct manipulations of buses_supported are not needed/possible anymore.

Note: Programmers without parallel/LPC/FWH chip support should not call
register_par_programmer().

Additional fixes:
Set max_rom_decode.parallel for drkaiser.
Remove abuse of programmer_map_flash_region in it85spi.
Annotate several FIXMEs in it85spi.

Corresponding to flashrom svn r1463.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
This commit is contained in:
Carl-Daniel Hailfinger 2011-11-09 23:40:00 +00:00
parent f382e352ac
commit eaacd2d4e7
22 changed files with 293 additions and 252 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
atahpt.c
View File

@ -40,6 +40,17 @@ const struct pcidev_status ata_hpt[] = {
{}, {},
}; };
static const struct par_programmer par_programmer_atahpt = {
.chip_readb = atahpt_chip_readb,
.chip_readw = fallback_chip_readw,
.chip_readl = fallback_chip_readl,
.chip_readn = fallback_chip_readn,
.chip_writeb = atahpt_chip_writeb,
.chip_writew = fallback_chip_writew,
.chip_writel = fallback_chip_writel,
.chip_writen = fallback_chip_writen,
};
static int atahpt_shutdown(void *data) static int atahpt_shutdown(void *data)
{ {
/* Flash access is disabled automatically by PCI restore. */ /* Flash access is disabled automatically by PCI restore. */
@ -61,10 +72,11 @@ int atahpt_init(void)
reg32 |= (1 << 24); reg32 |= (1 << 24);
rpci_write_long(pcidev_dev, REG_FLASH_ACCESS, reg32); rpci_write_long(pcidev_dev, REG_FLASH_ACCESS, reg32);
buses_supported = BUS_PARALLEL;
if (register_shutdown(atahpt_shutdown, NULL)) if (register_shutdown(atahpt_shutdown, NULL))
return 1; return 1;
register_par_programmer(&par_programmer_atahpt, BUS_PARALLEL);
return 0; return 0;
} }

2
board_enable.c
View File

@ -425,7 +425,7 @@ int it8705f_write_enable(uint8_t port)
/* Check if at least one flash segment is enabled. */ /* Check if at least one flash segment is enabled. */
if (tmp & 0xf0) { if (tmp & 0xf0) {
/* The IT8705F will respond to LPC cycles and translate them. */ /* The IT8705F will respond to LPC cycles and translate them. */
buses_supported = BUS_PARALLEL; internal_buses_supported = BUS_PARALLEL;
/* Flash ROM I/F Writes Enable */ /* Flash ROM I/F Writes Enable */
tmp |= 0x04; tmp |= 0x04;
msg_pdbg("Enabling IT8705F flash ROM interface write.\n"); msg_pdbg("Enabling IT8705F flash ROM interface write.\n");

34
chipset_enable.c
View File

@ -213,7 +213,7 @@ static int enable_flash_piix4(struct pci_dev *dev, const char *name)
uint16_t old, new; uint16_t old, new;
uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */ uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
buses_supported = BUS_PARALLEL; internal_buses_supported = BUS_PARALLEL;
old = pci_read_word(dev, xbcs); old = pci_read_word(dev, xbcs);
@ -303,7 +303,7 @@ static int enable_flash_ich_4e(struct pci_dev *dev, const char *name)
* FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and
* FB_DEC_EN2. * FB_DEC_EN2.
*/ */
buses_supported = BUS_FWH; internal_buses_supported = BUS_FWH;
return enable_flash_ich(dev, name, 0x4e); return enable_flash_ich(dev, name, 0x4e);
} }
@ -412,9 +412,9 @@ idsel_garbage_out:
msg_pdbg("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh); msg_pdbg("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh);
/* If we're called by enable_flash_ich_dc_spi, it will override /* If we're called by enable_flash_ich_dc_spi, it will override
* buses_supported anyway. * internal_buses_supported anyway.
*/ */
buses_supported = BUS_FWH; internal_buses_supported = BUS_FWH;
return enable_flash_ich(dev, name, 0xdc); return enable_flash_ich(dev, name, 0xdc);
} }
@ -434,7 +434,7 @@ static int enable_flash_poulsbo(struct pci_dev *dev, const char *name)
if (new != old) if (new != old)
rpci_write_byte(dev, 0xd9, new); rpci_write_byte(dev, 0xd9, new);
buses_supported = BUS_FWH; internal_buses_supported = BUS_FWH;
return 0; return 0;
} }
@ -468,12 +468,11 @@ static int enable_flash_tunnelcreek(struct pci_dev *dev, const char *name)
bnt = mmio_readl(rcrb + 0x3410); bnt = mmio_readl(rcrb + 0x3410);
if (bnt & 0x02) { if (bnt & 0x02) {
/* If strapped to LPC, no SPI initialization is required */ /* If strapped to LPC, no SPI initialization is required */
buses_supported = BUS_FWH; internal_buses_supported = BUS_FWH;
return 0; return 0;
} }
/* This adds BUS_SPI */ /* This adds BUS_SPI */
buses_supported = BUS_SPI;
if (ich_init_spi(dev, tmp, rcrb, 7) != 0) { if (ich_init_spi(dev, tmp, rcrb, 7) != 0) {
if (!ret) if (!ret)
ret = ERROR_NONFATAL; ret = ERROR_NONFATAL;
@ -556,7 +555,7 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
* time. At least not with our current code. So we prevent searching * time. At least not with our current code. So we prevent searching
* on ICH7 when the southbridge is strapped to LPC * on ICH7 when the southbridge is strapped to LPC
*/ */
buses_supported = BUS_FWH; internal_buses_supported = BUS_FWH;
if (ich_generation == CHIPSET_ICH7) { if (ich_generation == CHIPSET_ICH7) {
if (bbs == 0x03) { if (bbs == 0x03) {
/* If strapped to LPC, no further SPI initialization is /* If strapped to LPC, no further SPI initialization is
@ -564,7 +563,7 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
return ret; return ret;
} else { } else {
/* Disable LPC/FWH if strapped to PCI or SPI */ /* Disable LPC/FWH if strapped to PCI or SPI */
buses_supported = 0; internal_buses_supported = BUS_NONE;
} }
} }
@ -669,7 +668,7 @@ static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
#define CS5530_ENABLE_SA2320 (1 << 2) #define CS5530_ENABLE_SA2320 (1 << 2)
#define CS5530_ENABLE_SA20 (1 << 6) #define CS5530_ENABLE_SA20 (1 << 6)
buses_supported = BUS_PARALLEL; internal_buses_supported = BUS_PARALLEL;
/* Decode 0x000E0000-0x000FFFFF (128 kB), not just 64 kB, and /* Decode 0x000E0000-0x000FFFFF (128 kB), not just 64 kB, and
* decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 kB. * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 kB.
* FIXME: Should we really touch the low mapping below 1 MB? Flashrom * FIXME: Should we really touch the low mapping below 1 MB? Flashrom
@ -822,7 +821,7 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name)
(prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff)); (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
} }
buses_supported = BUS_LPC | BUS_FWH; internal_buses_supported = BUS_LPC | BUS_FWH;
ret = sb600_probe_spi(dev); ret = sb600_probe_spi(dev);
@ -916,7 +915,7 @@ static int enable_flash_osb4(struct pci_dev *dev, const char *name)
{ {
uint8_t tmp; uint8_t tmp;
buses_supported = BUS_PARALLEL; internal_buses_supported = BUS_PARALLEL;
tmp = INB(0xc06); tmp = INB(0xc06);
tmp |= 0x1; tmp |= 0x1;
@ -1016,7 +1015,7 @@ static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name)
switch ((val >> 5) & 0x3) { switch ((val >> 5) & 0x3) {
case 0x0: case 0x0:
ret = enable_flash_mcp55(dev, name); ret = enable_flash_mcp55(dev, name);
buses_supported = BUS_LPC; internal_buses_supported = BUS_LPC;
msg_pdbg("Flash bus type is LPC\n"); msg_pdbg("Flash bus type is LPC\n");
break; break;
case 0x2: case 0x2:
@ -1024,7 +1023,7 @@ static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name)
/* SPI is added in mcp6x_spi_init if it works. /* SPI is added in mcp6x_spi_init if it works.
* Do we really want to disable LPC in this case? * Do we really want to disable LPC in this case?
*/ */
buses_supported = BUS_NONE; internal_buses_supported = BUS_NONE;
msg_pdbg("Flash bus type is SPI\n"); msg_pdbg("Flash bus type is SPI\n");
msg_pinfo("SPI on this chipset is WIP. Please report any " msg_pinfo("SPI on this chipset is WIP. Please report any "
"success or failure by mailing us the verbose " "success or failure by mailing us the verbose "
@ -1032,7 +1031,7 @@ static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name)
break; break;
default: default:
/* Should not happen. */ /* Should not happen. */
buses_supported = BUS_NONE; internal_buses_supported = BUS_NONE;
msg_pdbg("Flash bus type is unknown (none)\n"); msg_pdbg("Flash bus type is unknown (none)\n");
msg_pinfo("Something went wrong with bus type detection.\n"); msg_pinfo("Something went wrong with bus type detection.\n");
goto out_msg; goto out_msg;
@ -1325,7 +1324,6 @@ int chipset_flash_enable(void)
struct pci_dev *dev = NULL; struct pci_dev *dev = NULL;
int ret = -2; /* Nothing! */ int ret = -2; /* Nothing! */
int i; int i;
char *s;
/* Now let's try to find the chipset we have... */ /* Now let's try to find the chipset we have... */
for (i = 0; chipset_enables[i].vendor_name != NULL; i++) { for (i = 0; chipset_enables[i].vendor_name != NULL; i++) {
@ -1377,9 +1375,5 @@ int chipset_flash_enable(void)
} }
} }
s = flashbuses_to_text(buses_supported);
msg_pinfo("This chipset supports the following protocols: %s.\n", s);
free(s);
return ret; return ret;
} }

4
cli_classic.c
View File

@ -443,6 +443,10 @@ int main(int argc, char *argv[])
ret = 1; ret = 1;
goto out_shutdown; goto out_shutdown;
} }
tempstr = flashbuses_to_text(buses_supported);
msg_pdbg("This programmer supports the following protocols: %s.\n",
tempstr);
free(tempstr);
for (i = 0; i < ARRAY_SIZE(flashes); i++) { for (i = 0; i < ARRAY_SIZE(flashes); i++) {
startchip = probe_flash(startchip, &flashes[i], 0); startchip = probe_flash(startchip, &flashes[i], 0);

17
drkaiser.c
View File

@ -39,6 +39,17 @@ const struct pcidev_status drkaiser_pcidev[] = {
static uint8_t *drkaiser_bar; static uint8_t *drkaiser_bar;
static const struct par_programmer par_programmer_drkaiser = {
.chip_readb = drkaiser_chip_readb,
.chip_readw = fallback_chip_readw,
.chip_readl = fallback_chip_readl,
.chip_readn = fallback_chip_readn,
.chip_writeb = drkaiser_chip_writeb,
.chip_writew = fallback_chip_writew,
.chip_writel = fallback_chip_writel,
.chip_writen = fallback_chip_writen,
};
static int drkaiser_shutdown(void *data) static int drkaiser_shutdown(void *data)
{ {
physunmap(drkaiser_bar, DRKAISER_MEMMAP_SIZE); physunmap(drkaiser_bar, DRKAISER_MEMMAP_SIZE);
@ -64,10 +75,12 @@ int drkaiser_init(void)
drkaiser_bar = physmap("Dr. Kaiser PC-Waechter flash memory", drkaiser_bar = physmap("Dr. Kaiser PC-Waechter flash memory",
addr, DRKAISER_MEMMAP_SIZE); addr, DRKAISER_MEMMAP_SIZE);
buses_supported = BUS_PARALLEL;
if (register_shutdown(drkaiser_shutdown, NULL)) if (register_shutdown(drkaiser_shutdown, NULL))
return 1; return 1;
max_rom_decode.parallel = 128 * 1024;
register_par_programmer(&par_programmer_drkaiser, BUS_PARALLEL);
return 0; return 0;
} }

33
dummyflasher.c
View File

@ -75,6 +75,19 @@ static const struct spi_programmer spi_programmer_dummyflasher = {
.write_256 = dummy_spi_write_256, .write_256 = dummy_spi_write_256,
}; };
static const struct par_programmer par_programmer_dummy = {
.chip_readb = dummy_chip_readb,
.chip_readw = dummy_chip_readw,
.chip_readl = dummy_chip_readl,
.chip_readn = dummy_chip_readn,
.chip_writeb = dummy_chip_writeb,
.chip_writew = dummy_chip_writew,
.chip_writel = dummy_chip_writel,
.chip_writen = dummy_chip_writen,
};
enum chipbustype dummy_buses_supported = BUS_NONE;
static int dummy_shutdown(void *data) static int dummy_shutdown(void *data)
{ {
msg_pspew("%s\n", __func__); msg_pspew("%s\n", __func__);
@ -108,24 +121,24 @@ int dummy_init(void)
/* Convert the parameters to lowercase. */ /* Convert the parameters to lowercase. */
tolower_string(bustext); tolower_string(bustext);
buses_supported = BUS_NONE; dummy_buses_supported = BUS_NONE;
if (strstr(bustext, "parallel")) { if (strstr(bustext, "parallel")) {
buses_supported |= BUS_PARALLEL; dummy_buses_supported |= BUS_PARALLEL;
msg_pdbg("Enabling support for %s flash.\n", "parallel"); msg_pdbg("Enabling support for %s flash.\n", "parallel");
} }
if (strstr(bustext, "lpc")) { if (strstr(bustext, "lpc")) {
buses_supported |= BUS_LPC; dummy_buses_supported |= BUS_LPC;
msg_pdbg("Enabling support for %s flash.\n", "LPC"); msg_pdbg("Enabling support for %s flash.\n", "LPC");
} }
if (strstr(bustext, "fwh")) { if (strstr(bustext, "fwh")) {
buses_supported |= BUS_FWH; dummy_buses_supported |= BUS_FWH;
msg_pdbg("Enabling support for %s flash.\n", "FWH"); msg_pdbg("Enabling support for %s flash.\n", "FWH");
} }
if (strstr(bustext, "spi")) { if (strstr(bustext, "spi")) {
register_spi_programmer(&spi_programmer_dummyflasher); dummy_buses_supported |= BUS_SPI;
msg_pdbg("Enabling support for %s flash.\n", "SPI"); msg_pdbg("Enabling support for %s flash.\n", "SPI");
} }
if (buses_supported == BUS_NONE) if (dummy_buses_supported == BUS_NONE)
msg_pdbg("Support for all flash bus types disabled.\n"); msg_pdbg("Support for all flash bus types disabled.\n");
free(bustext); free(bustext);
@ -226,6 +239,14 @@ dummy_init_out:
free(flashchip_contents); free(flashchip_contents);
return 1; return 1;
} }
if (dummy_buses_supported & (BUS_PARALLEL | BUS_LPC | BUS_FWH))
register_par_programmer(&par_programmer_dummy,
dummy_buses_supported &
(BUS_PARALLEL | BUS_LPC |
BUS_FWH));
if (dummy_buses_supported & BUS_SPI)
register_spi_programmer(&spi_programmer_dummyflasher);
return 0; return 0;
} }

168
flashrom.c
View File

@ -68,14 +68,6 @@ const struct programmer_entry programmer_table[] = {
.init = internal_init, .init = internal_init,
.map_flash_region = physmap, .map_flash_region = physmap,
.unmap_flash_region = physunmap, .unmap_flash_region = physunmap,
.chip_readb = internal_chip_readb,
.chip_readw = internal_chip_readw,
.chip_readl = internal_chip_readl,
.chip_readn = internal_chip_readn,
.chip_writeb = internal_chip_writeb,
.chip_writew = internal_chip_writew,
.chip_writel = internal_chip_writel,
.chip_writen = fallback_chip_writen,
.delay = internal_delay, .delay = internal_delay,
}, },
#endif #endif
@ -86,14 +78,6 @@ const struct programmer_entry programmer_table[] = {
.init = dummy_init, .init = dummy_init,
.map_flash_region = dummy_map, .map_flash_region = dummy_map,
.unmap_flash_region = dummy_unmap, .unmap_flash_region = dummy_unmap,
.chip_readb = dummy_chip_readb,
.chip_readw = dummy_chip_readw,
.chip_readl = dummy_chip_readl,
.chip_readn = dummy_chip_readn,
.chip_writeb = dummy_chip_writeb,
.chip_writew = dummy_chip_writew,
.chip_writel = dummy_chip_writel,
.chip_writen = dummy_chip_writen,
.delay = internal_delay, .delay = internal_delay,
}, },
#endif #endif
@ -104,14 +88,6 @@ const struct programmer_entry programmer_table[] = {
.init = nic3com_init, .init = nic3com_init,
.map_flash_region = fallback_map, .map_flash_region = fallback_map,
.unmap_flash_region = fallback_unmap, .unmap_flash_region = fallback_unmap,
.chip_readb = nic3com_chip_readb,
.chip_readw = fallback_chip_readw,
.chip_readl = fallback_chip_readl,
.chip_readn = fallback_chip_readn,
.chip_writeb = nic3com_chip_writeb,
.chip_writew = fallback_chip_writew,
.chip_writel = fallback_chip_writel,
.chip_writen = fallback_chip_writen,
.delay = internal_delay, .delay = internal_delay,
}, },
#endif #endif
@ -124,14 +100,6 @@ const struct programmer_entry programmer_table[] = {
.init = nicrealtek_init, .init = nicrealtek_init,
.map_flash_region = fallback_map, .map_flash_region = fallback_map,
.unmap_flash_region = fallback_unmap, .unmap_flash_region = fallback_unmap,
.chip_readb = nicrealtek_chip_readb,
.chip_readw = fallback_chip_readw,
.chip_readl = fallback_chip_readl,
.chip_readn = fallback_chip_readn,
.chip_writeb = nicrealtek_chip_writeb,
.chip_writew = fallback_chip_writew,
.chip_writel = fallback_chip_writel,
.chip_writen = fallback_chip_writen,
.delay = internal_delay, .delay = internal_delay,
}, },
#endif #endif
@ -142,14 +110,6 @@ const struct programmer_entry programmer_table[] = {
.init = nicnatsemi_init, .init = nicnatsemi_init,
.map_flash_region = fallback_map, .map_flash_region = fallback_map,
.unmap_flash_region = fallback_unmap, .unmap_flash_region = fallback_unmap,
.chip_readb = nicnatsemi_chip_readb,
.chip_readw = fallback_chip_readw,
.chip_readl = fallback_chip_readl,
.chip_readn = fallback_chip_readn,
.chip_writeb = nicnatsemi_chip_writeb,
.chip_writew = fallback_chip_writew,
.chip_writel = fallback_chip_writel,
.chip_writen = fallback_chip_writen,
.delay = internal_delay, .delay = internal_delay,
}, },
#endif #endif
@ -160,14 +120,6 @@ const struct programmer_entry programmer_table[] = {
.init = gfxnvidia_init, .init = gfxnvidia_init,
.map_flash_region = fallback_map, .map_flash_region = fallback_map,
.unmap_flash_region = fallback_unmap, .unmap_flash_region = fallback_unmap,
.chip_readb = gfxnvidia_chip_readb,
.chip_readw = fallback_chip_readw,
.chip_readl = fallback_chip_readl,
.chip_readn = fallback_chip_readn,
.chip_writeb = gfxnvidia_chip_writeb,
.chip_writew = fallback_chip_writew,
.chip_writel = fallback_chip_writel,
.chip_writen = fallback_chip_writen,
.delay = internal_delay, .delay = internal_delay,
}, },
#endif #endif
@ -178,14 +130,6 @@ const struct programmer_entry programmer_table[] = {
.init = drkaiser_init, .init = drkaiser_init,
.map_flash_region = fallback_map, .map_flash_region = fallback_map,
.unmap_flash_region = fallback_unmap, .unmap_flash_region = fallback_unmap,
.chip_readb = drkaiser_chip_readb,
.chip_readw = fallback_chip_readw,
.chip_readl = fallback_chip_readl,
.chip_readn = fallback_chip_readn,
.chip_writeb = drkaiser_chip_writeb,
.chip_writew = fallback_chip_writew,
.chip_writel = fallback_chip_writel,
.chip_writen = fallback_chip_writen,
.delay = internal_delay, .delay = internal_delay,
}, },
#endif #endif
@ -196,14 +140,6 @@ const struct programmer_entry programmer_table[] = {
.init = satasii_init, .init = satasii_init,
.map_flash_region = fallback_map, .map_flash_region = fallback_map,
.unmap_flash_region = fallback_unmap, .unmap_flash_region = fallback_unmap,
.chip_readb = satasii_chip_readb,
.chip_readw = fallback_chip_readw,
.chip_readl = fallback_chip_readl,
.chip_readn = fallback_chip_readn,
.chip_writeb = satasii_chip_writeb,
.chip_writew = fallback_chip_writew,
.chip_writel = fallback_chip_writel,
.chip_writen = fallback_chip_writen,
.delay = internal_delay, .delay = internal_delay,
}, },
#endif #endif
@ -214,14 +150,6 @@ const struct programmer_entry programmer_table[] = {
.init = atahpt_init, .init = atahpt_init,
.map_flash_region = fallback_map, .map_flash_region = fallback_map,
.unmap_flash_region = fallback_unmap, .unmap_flash_region = fallback_unmap,
.chip_readb = atahpt_chip_readb,
.chip_readw = fallback_chip_readw,
.chip_readl = fallback_chip_readl,
.chip_readn = fallback_chip_readn,
.chip_writeb = atahpt_chip_writeb,
.chip_writew = fallback_chip_writew,
.chip_writel = fallback_chip_writel,
.chip_writen = fallback_chip_writen,
.delay = internal_delay, .delay = internal_delay,
}, },
#endif #endif
@ -232,14 +160,6 @@ const struct programmer_entry programmer_table[] = {
.init = ft2232_spi_init, .init = ft2232_spi_init,
.map_flash_region = fallback_map, .map_flash_region = fallback_map,
.unmap_flash_region = fallback_unmap, .unmap_flash_region = fallback_unmap,
.chip_readb = noop_chip_readb,
.chip_readw = fallback_chip_readw,
.chip_readl = fallback_chip_readl,
.chip_readn = fallback_chip_readn,
.chip_writeb = noop_chip_writeb,
.chip_writew = fallback_chip_writew,
.chip_writel = fallback_chip_writel,
.chip_writen = fallback_chip_writen,
.delay = internal_delay, .delay = internal_delay,
}, },
#endif #endif
@ -250,14 +170,6 @@ const struct programmer_entry programmer_table[] = {
.init = serprog_init, .init = serprog_init,
.map_flash_region = fallback_map, .map_flash_region = fallback_map,
.unmap_flash_region = fallback_unmap, .unmap_flash_region = fallback_unmap,
.chip_readb = serprog_chip_readb,
.chip_readw = fallback_chip_readw,
.chip_readl = fallback_chip_readl,
.chip_readn = serprog_chip_readn,
.chip_writeb = serprog_chip_writeb,
.chip_writew = fallback_chip_writew,
.chip_writel = fallback_chip_writel,
.chip_writen = fallback_chip_writen,
.delay = serprog_delay, .delay = serprog_delay,
}, },
#endif #endif
@ -268,14 +180,6 @@ const struct programmer_entry programmer_table[] = {
.init = buspirate_spi_init, .init = buspirate_spi_init,
.map_flash_region = fallback_map, .map_flash_region = fallback_map,
.unmap_flash_region = fallback_unmap, .unmap_flash_region = fallback_unmap,
.chip_readb = noop_chip_readb,
.chip_readw = fallback_chip_readw,
.chip_readl = fallback_chip_readl,
.chip_readn = fallback_chip_readn,
.chip_writeb = noop_chip_writeb,
.chip_writew = fallback_chip_writew,
.chip_writel = fallback_chip_writel,
.chip_writen = fallback_chip_writen,
.delay = internal_delay, .delay = internal_delay,
}, },
#endif #endif
@ -286,14 +190,6 @@ const struct programmer_entry programmer_table[] = {
.init = dediprog_init, .init = dediprog_init,
.map_flash_region = fallback_map, .map_flash_region = fallback_map,
.unmap_flash_region = fallback_unmap, .unmap_flash_region = fallback_unmap,
.chip_readb = noop_chip_readb,
.chip_readw = fallback_chip_readw,
.chip_readl = fallback_chip_readl,
.chip_readn = fallback_chip_readn,
.chip_writeb = noop_chip_writeb,
.chip_writew = fallback_chip_writew,
.chip_writel = fallback_chip_writel,
.chip_writen = fallback_chip_writen,
.delay = internal_delay, .delay = internal_delay,
}, },
#endif #endif
@ -304,14 +200,6 @@ const struct programmer_entry programmer_table[] = {
.init = rayer_spi_init, .init = rayer_spi_init,
.map_flash_region = fallback_map, .map_flash_region = fallback_map,
.unmap_flash_region = fallback_unmap, .unmap_flash_region = fallback_unmap,
.chip_readb = noop_chip_readb,
.chip_readw = fallback_chip_readw,
.chip_readl = fallback_chip_readl,
.chip_readn = fallback_chip_readn,
.chip_writeb = noop_chip_writeb,
.chip_writew = fallback_chip_writew,
.chip_writel = fallback_chip_writel,
.chip_writen = fallback_chip_writen,
.delay = internal_delay, .delay = internal_delay,
}, },
#endif #endif
@ -322,14 +210,6 @@ const struct programmer_entry programmer_table[] = {
.init = nicintel_init, .init = nicintel_init,
.map_flash_region = fallback_map, .map_flash_region = fallback_map,
.unmap_flash_region = fallback_unmap, .unmap_flash_region = fallback_unmap,
.chip_readb = nicintel_chip_readb,
.chip_readw = fallback_chip_readw,
.chip_readl = fallback_chip_readl,
.chip_readn = fallback_chip_readn,
.chip_writeb = nicintel_chip_writeb,
.chip_writew = fallback_chip_writew,
.chip_writel = fallback_chip_writel,
.chip_writen = fallback_chip_writen,
.delay = internal_delay, .delay = internal_delay,
}, },
#endif #endif
@ -340,14 +220,6 @@ const struct programmer_entry programmer_table[] = {
.init = nicintel_spi_init, .init = nicintel_spi_init,
.map_flash_region = fallback_map, .map_flash_region = fallback_map,
.unmap_flash_region = fallback_unmap, .unmap_flash_region = fallback_unmap,
.chip_readb = noop_chip_readb,
.chip_readw = fallback_chip_readw,
.chip_readl = fallback_chip_readl,
.chip_readn = fallback_chip_readn,
.chip_writeb = noop_chip_writeb,
.chip_writew = fallback_chip_writew,
.chip_writel = fallback_chip_writel,
.chip_writen = fallback_chip_writen,
.delay = internal_delay, .delay = internal_delay,
}, },
#endif #endif
@ -358,14 +230,6 @@ const struct programmer_entry programmer_table[] = {
.init = ogp_spi_init, .init = ogp_spi_init,
.map_flash_region = fallback_map, .map_flash_region = fallback_map,
.unmap_flash_region = fallback_unmap, .unmap_flash_region = fallback_unmap,
.chip_readb = noop_chip_readb,
.chip_readw = fallback_chip_readw,
.chip_readl = fallback_chip_readl,
.chip_readn = fallback_chip_readn,
.chip_writeb = noop_chip_writeb,
.chip_writew = fallback_chip_writew,
.chip_writel = fallback_chip_writel,
.chip_writen = fallback_chip_writen,
.delay = internal_delay, .delay = internal_delay,
}, },
#endif #endif
@ -376,14 +240,6 @@ const struct programmer_entry programmer_table[] = {
.init = satamv_init, .init = satamv_init,
.map_flash_region = fallback_map, .map_flash_region = fallback_map,
.unmap_flash_region = fallback_unmap, .unmap_flash_region = fallback_unmap,
.chip_readb = satamv_chip_readb,
.chip_readw = fallback_chip_readw,
.chip_readl = fallback_chip_readl,
.chip_readn = fallback_chip_readn,
.chip_writeb = satamv_chip_writeb,
.chip_writew = fallback_chip_writew,
.chip_writel = fallback_chip_writel,
.chip_writen = fallback_chip_writen,
.delay = internal_delay, .delay = internal_delay,
}, },
#endif #endif
@ -394,14 +250,6 @@ const struct programmer_entry programmer_table[] = {
.init = linux_spi_init, .init = linux_spi_init,
.map_flash_region = fallback_map, .map_flash_region = fallback_map,
.unmap_flash_region = fallback_unmap, .unmap_flash_region = fallback_unmap,
.chip_readb = noop_chip_readb,
.chip_readw = fallback_chip_readw,
.chip_readl = fallback_chip_readl,
.chip_readn = fallback_chip_readn,
.chip_writeb = noop_chip_writeb,
.chip_writew = fallback_chip_writew,
.chip_writel = fallback_chip_writel,
.chip_writen = fallback_chip_writen,
.delay = internal_delay, .delay = internal_delay,
}, },
#endif #endif
@ -513,42 +361,42 @@ void programmer_unmap_flash_region(void *virt_addr, size_t len)
void chip_writeb(uint8_t val, chipaddr addr) void chip_writeb(uint8_t val, chipaddr addr)
{ {
programmer_table[programmer].chip_writeb(val, addr); par_programmer->chip_writeb(val, addr);
} }
void chip_writew(uint16_t val, chipaddr addr) void chip_writew(uint16_t val, chipaddr addr)
{ {
programmer_table[programmer].chip_writew(val, addr); par_programmer->chip_writew(val, addr);
} }
void chip_writel(uint32_t val, chipaddr addr) void chip_writel(uint32_t val, chipaddr addr)
{ {
programmer_table[programmer].chip_writel(val, addr); par_programmer->chip_writel(val, addr);
} }
void chip_writen(uint8_t *buf, chipaddr addr, size_t len) void chip_writen(uint8_t *buf, chipaddr addr, size_t len)
{ {
programmer_table[programmer].chip_writen(buf, addr, len); par_programmer->chip_writen(buf, addr, len);
} }
uint8_t chip_readb(const chipaddr addr) uint8_t chip_readb(const chipaddr addr)
{ {
return programmer_table[programmer].chip_readb(addr); return par_programmer->chip_readb(addr);
} }
uint16_t chip_readw(const chipaddr addr) uint16_t chip_readw(const chipaddr addr)
{ {
return programmer_table[programmer].chip_readw(addr); return par_programmer->chip_readw(addr);
} }
uint32_t chip_readl(const chipaddr addr) uint32_t chip_readl(const chipaddr addr)
{ {
return programmer_table[programmer].chip_readl(addr); return par_programmer->chip_readl(addr);
} }
void chip_readn(uint8_t *buf, chipaddr addr, size_t len) void chip_readn(uint8_t *buf, chipaddr addr, size_t len)
{ {
programmer_table[programmer].chip_readn(buf, addr, len); par_programmer->chip_readn(buf, addr, len);
} }
void programmer_delay(int usecs) void programmer_delay(int usecs)

14
gfxnvidia.c
View File

@ -61,6 +61,17 @@ const struct pcidev_status gfx_nvidia[] = {
{}, {},
}; };
static const struct par_programmer par_programmer_gfxnvidia = {
.chip_readb = gfxnvidia_chip_readb,
.chip_readw = fallback_chip_readw,
.chip_readl = fallback_chip_readl,
.chip_readn = fallback_chip_readn,
.chip_writeb = gfxnvidia_chip_writeb,
.chip_writew = fallback_chip_writew,
.chip_writel = fallback_chip_writel,
.chip_writen = fallback_chip_writen,
};
static int gfxnvidia_shutdown(void *data) static int gfxnvidia_shutdown(void *data)
{ {
physunmap(nvidia_bar, GFXNVIDIA_MEMMAP_SIZE); physunmap(nvidia_bar, GFXNVIDIA_MEMMAP_SIZE);
@ -94,10 +105,9 @@ int gfxnvidia_init(void)
reg32 &= ~(1 << 0); reg32 &= ~(1 << 0);
rpci_write_long(pcidev_dev, 0x50, reg32); rpci_write_long(pcidev_dev, 0x50, reg32);
buses_supported = BUS_PARALLEL;
/* Write/erase doesn't work. */ /* Write/erase doesn't work. */
programmer_may_write = 0; programmer_may_write = 0;
register_par_programmer(&par_programmer_gfxnvidia, BUS_PARALLEL);
return 0; return 0;
} }

2
ichspi.c
View File

@ -1796,7 +1796,7 @@ int via_init_spi(struct pci_dev *dev)
ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70);
/* Not sure if it speaks all these bus protocols. */ /* Not sure if it speaks all these bus protocols. */
buses_supported = BUS_LPC | BUS_FWH; internal_buses_supported = BUS_LPC | BUS_FWH;
ich_generation = CHIPSET_ICH7; ich_generation = CHIPSET_ICH7;
register_spi_programmer(&spi_programmer_via); register_spi_programmer(&spi_programmer_via);

19
internal.c
View File

@ -127,6 +127,19 @@ int register_superio(struct superio s)
int is_laptop = 0; int is_laptop = 0;
int laptop_ok = 0; int laptop_ok = 0;
static const struct par_programmer par_programmer_internal = {
.chip_readb = internal_chip_readb,
.chip_readw = internal_chip_readw,
.chip_readl = internal_chip_readl,
.chip_readn = internal_chip_readn,
.chip_writeb = internal_chip_writeb,
.chip_writew = internal_chip_writew,
.chip_writel = internal_chip_writel,
.chip_writen = fallback_chip_writen,
};
enum chipbustype internal_buses_supported = BUS_NONE;
static int internal_shutdown(void *data) static int internal_shutdown(void *data)
{ {
release_io_perms(); release_io_perms();
@ -191,9 +204,10 @@ int internal_init(void)
return 1; return 1;
/* Default to Parallel/LPC/FWH flash devices. If a known host controller /* Default to Parallel/LPC/FWH flash devices. If a known host controller
* is found, the init routine sets the buses_supported bitfield. * is found, the host controller init routine sets the
* internal_buses_supported bitfield.
*/ */
buses_supported = BUS_NONSPI; internal_buses_supported = BUS_NONSPI;
/* Initialize PCI access for flash enables */ /* Initialize PCI access for flash enables */
pacc = pci_alloc(); /* Get the pci_access structure */ pacc = pci_alloc(); /* Get the pci_access structure */
@ -287,6 +301,7 @@ int internal_init(void)
* Besides that, we don't check the board enable return code either. * Besides that, we don't check the board enable return code either.
*/ */
#if defined(__i386__) || defined(__x86_64__) || defined (__mips) #if defined(__i386__) || defined(__x86_64__) || defined (__mips)
register_par_programmer(&par_programmer_internal, internal_buses_supported);
return 0; return 0;
#else #else
msg_perr("Your platform is not supported yet for the internal " msg_perr("Your platform is not supported yet for the internal "

26
it85spi.c
View File

@ -257,8 +257,10 @@ static int it85xx_spi_common_init(struct superio s)
INDIRECT_A3(shm_io_base, (base >> 24)); INDIRECT_A3(shm_io_base, (base >> 24));
#endif #endif
#ifdef LPC_MEMORY #ifdef LPC_MEMORY
base = (chipaddr)programmer_map_flash_region("it85 communication", /* FIXME: We should block accessing that region for anything else.
0xFFFFF000, 0x1000); * Major TODO here, and it will be a lot of work.
*/
base = (chipaddr)physmap("it85 communication", 0xFFFFF000, 0x1000);
msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__, msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__,
(unsigned int)base); (unsigned int)base);
ce_high = (unsigned char *)(base + 0xE00); /* 0xFFFFFE00 */ ce_high = (unsigned char *)(base + 0xE00); /* 0xFFFFFE00 */
@ -285,18 +287,26 @@ int it85xx_spi_init(struct superio s)
{ {
int ret; int ret;
if (!(buses_supported & BUS_FWH)) { if (!(internal_buses_supported & BUS_FWH)) {
msg_pdbg("%s():%d buses not support FWH\n", __func__, __LINE__); msg_pdbg("%s():%d buses not support FWH\n", __func__, __LINE__);
return 1; return 1;
} }
ret = it85xx_spi_common_init(s); ret = it85xx_spi_common_init(s);
msg_pdbg("FWH: %s():%d ret=%d\n", __func__, __LINE__, ret); msg_pdbg("FWH: %s():%d ret=%d\n", __func__, __LINE__, ret);
if (!ret) { if (!ret) {
msg_pdbg("%s():%d buses_supported=0x%x\n", __func__, __LINE__, msg_pdbg("%s: internal_buses_supported=0x%x\n", __func__,
buses_supported); internal_buses_supported);
if (buses_supported & BUS_FWH) /* Check for FWH because IT85 listens to FWH cycles.
msg_pdbg("Overriding chipset SPI with IT85 FWH|SPI.\n"); * FIXME: The big question is whether FWH cycles are necessary
/* Really leave FWH enabled? */ * for communication even if LPC_IO is defined.
*/
if (internal_buses_supported & BUS_FWH)
msg_pdbg("Registering IT85 SPI.\n");
/* FIXME: Really leave FWH enabled? We can't use this region
* anymore since accessing it would mess up IT85 communication.
* If we decide to disable FWH for this region, we should print
* a debug message about it.
*/
/* Set this as SPI controller. */ /* Set this as SPI controller. */
register_spi_programmer(&spi_programmer_it85xx); register_spi_programmer(&spi_programmer_it85xx);
} }

2
it87spi.c
View File

@ -192,7 +192,7 @@ static uint16_t it87spi_probe(uint16_t port)
free(portpos); free(portpos);
exit_conf_mode_ite(port); exit_conf_mode_ite(port);
it8716f_flashport = flashport; it8716f_flashport = flashport;
if (buses_supported & BUS_SPI) if (internal_buses_supported & BUS_SPI)
msg_pdbg("Overriding chipset SPI with IT87 SPI.\n"); msg_pdbg("Overriding chipset SPI with IT87 SPI.\n");
/* FIXME: Add the SPI bus or replace the other buses with it? */ /* FIXME: Add the SPI bus or replace the other buses with it? */
register_spi_programmer(&spi_programmer_it87xx); register_spi_programmer(&spi_programmer_it87xx);

18
nic3com.c
View File

@ -55,6 +55,17 @@ const struct pcidev_status nics_3com[] = {
{}, {},
}; };
static const struct par_programmer par_programmer_nic3com = {
.chip_readb = nic3com_chip_readb,
.chip_readw = fallback_chip_readw,
.chip_readl = fallback_chip_readl,
.chip_readn = fallback_chip_readn,
.chip_writeb = nic3com_chip_writeb,
.chip_writew = fallback_chip_writew,
.chip_writel = fallback_chip_writel,
.chip_writen = fallback_chip_writen,
};
static int nic3com_shutdown(void *data) static int nic3com_shutdown(void *data)
{ {
/* 3COM 3C90xB cards need a special fixup. */ /* 3COM 3C90xB cards need a special fixup. */
@ -96,11 +107,12 @@ int nic3com_init(void)
*/ */
OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS); OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS);
buses_supported = BUS_PARALLEL;
max_rom_decode.parallel = 128 * 1024;
if (register_shutdown(nic3com_shutdown, NULL)) if (register_shutdown(nic3com_shutdown, NULL))
return 1; return 1;
max_rom_decode.parallel = 128 * 1024;
register_par_programmer(&par_programmer_nic3com, BUS_PARALLEL);
return 0; return 0;
} }

14
nicintel.c
View File

@ -43,6 +43,17 @@ const struct pcidev_status nics_intel[] = {
#define CSR_FCR 0x0c #define CSR_FCR 0x0c
static const struct par_programmer par_programmer_nicintel = {
.chip_readb = nicintel_chip_readb,
.chip_readw = fallback_chip_readw,
.chip_readl = fallback_chip_readl,
.chip_readn = fallback_chip_readn,
.chip_writeb = nicintel_chip_writeb,
.chip_writew = fallback_chip_writew,
.chip_writel = fallback_chip_writel,
.chip_writen = fallback_chip_writen,
};
static int nicintel_shutdown(void *data) static int nicintel_shutdown(void *data)
{ {
physunmap(nicintel_control_bar, NICINTEL_CONTROL_MEMMAP_SIZE); physunmap(nicintel_control_bar, NICINTEL_CONTROL_MEMMAP_SIZE);
@ -93,9 +104,8 @@ int nicintel_init(void)
*/ */
pci_rmmio_writew(0x0001, nicintel_control_bar + CSR_FCR); pci_rmmio_writew(0x0001, nicintel_control_bar + CSR_FCR);
buses_supported = BUS_PARALLEL;
max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE; max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE;
register_par_programmer(&par_programmer_nicintel, BUS_PARALLEL);
return 0; return 0;

17
nicnatsemi.c
View File

@ -35,6 +35,17 @@ const struct pcidev_status nics_natsemi[] = {
{}, {},
}; };
static const struct par_programmer par_programmer_nicnatsemi = {
.chip_readb = nicnatsemi_chip_readb,
.chip_readw = fallback_chip_readw,
.chip_readl = fallback_chip_readl,
.chip_readn = fallback_chip_readn,
.chip_writeb = nicnatsemi_chip_writeb,
.chip_writew = fallback_chip_writew,
.chip_writel = fallback_chip_writel,
.chip_writen = fallback_chip_writen,
};
static int nicnatsemi_shutdown(void *data) static int nicnatsemi_shutdown(void *data)
{ {
pci_cleanup(pacc); pci_cleanup(pacc);
@ -48,7 +59,8 @@ int nicnatsemi_init(void)
io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_natsemi); io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_natsemi);
buses_supported = BUS_PARALLEL; if (register_shutdown(nicnatsemi_shutdown, NULL))
return 1;
/* The datasheet shows address lines MA0-MA16 in one place and MA0-MA15 /* The datasheet shows address lines MA0-MA16 in one place and MA0-MA15
* in another. My NIC has MA16 connected to A16 on the boot ROM socket * in another. My NIC has MA16 connected to A16 on the boot ROM socket
@ -57,9 +69,8 @@ int nicnatsemi_init(void)
* functions below wants to be 0x0000FFFF. * functions below wants to be 0x0000FFFF.
*/ */
max_rom_decode.parallel = 131072; max_rom_decode.parallel = 131072;
register_par_programmer(&par_programmer_nicnatsemi, BUS_PARALLEL);
if (register_shutdown(nicnatsemi_shutdown, NULL))
return 1;
return 0; return 0;
} }

16
nicrealtek.c
View File

@ -36,6 +36,17 @@ const struct pcidev_status nics_realtek[] = {
{}, {},
}; };
static const struct par_programmer par_programmer_nicrealtek = {
.chip_readb = nicrealtek_chip_readb,
.chip_readw = fallback_chip_readw,
.chip_readl = fallback_chip_readl,
.chip_readn = fallback_chip_readn,
.chip_writeb = nicrealtek_chip_writeb,
.chip_writew = fallback_chip_writew,
.chip_writel = fallback_chip_writel,
.chip_writen = fallback_chip_writen,
};
static int nicrealtek_shutdown(void *data) static int nicrealtek_shutdown(void *data)
{ {
/* FIXME: We forgot to disable software access again. */ /* FIXME: We forgot to disable software access again. */
@ -50,10 +61,11 @@ int nicrealtek_init(void)
io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_realtek); io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_realtek);
buses_supported = BUS_PARALLEL;
if (register_shutdown(nicrealtek_shutdown, NULL)) if (register_shutdown(nicrealtek_shutdown, NULL))
return 1; return 1;
register_par_programmer(&par_programmer_nicrealtek, BUS_PARALLEL);
return 0; return 0;
} }

20
programmer.c
View File

@ -19,6 +19,20 @@
*/ */
#include "flash.h" #include "flash.h"
#include "programmer.h"
static const struct par_programmer par_programmer_none = {
.chip_readb = noop_chip_readb,
.chip_readw = fallback_chip_readw,
.chip_readl = fallback_chip_readl,
.chip_readn = fallback_chip_readn,
.chip_writeb = noop_chip_writeb,
.chip_writew = fallback_chip_writew,
.chip_writel = fallback_chip_writel,
.chip_writen = fallback_chip_writen,
};
const struct par_programmer *par_programmer = &par_programmer_none;
/* No-op shutdown() for programmers which don't need special handling */ /* No-op shutdown() for programmers which don't need special handling */
int noop_shutdown(void) int noop_shutdown(void)
@ -96,3 +110,9 @@ void fallback_chip_readn(uint8_t *buf, chipaddr addr, size_t len)
buf[i] = chip_readb(addr + i); buf[i] = chip_readb(addr + i);
return; return;
} }
void register_par_programmer(const struct par_programmer *pgm, const enum chipbustype buses)
{
par_programmer = pgm;
buses_supported |= buses;
}

25
programmer.h
View File

@ -97,14 +97,6 @@ struct programmer_entry {
size_t len); size_t len);
void (*unmap_flash_region) (void *virt_addr, size_t len); void (*unmap_flash_region) (void *virt_addr, size_t len);
void (*chip_writeb) (uint8_t val, chipaddr addr);
void (*chip_writew) (uint16_t val, chipaddr addr);
void (*chip_writel) (uint32_t val, chipaddr addr);
void (*chip_writen) (uint8_t *buf, chipaddr addr, size_t len);
uint8_t (*chip_readb) (const chipaddr addr);
uint16_t (*chip_readw) (const chipaddr addr);
uint32_t (*chip_readl) (const chipaddr addr);
void (*chip_readn) (uint8_t *buf, const chipaddr addr, size_t len);
void (*delay) (int usecs); void (*delay) (int usecs);
}; };
@ -306,6 +298,7 @@ extern int force_boardenable;
extern int force_boardmismatch; extern int force_boardmismatch;
void probe_superio(void); void probe_superio(void);
int register_superio(struct superio s); int register_superio(struct superio s);
extern enum chipbustype internal_buses_supported;
int internal_init(void); int internal_init(void);
void internal_chip_writeb(uint8_t val, chipaddr addr); void internal_chip_writeb(uint8_t val, chipaddr addr);
void internal_chip_writew(uint16_t val, chipaddr addr); void internal_chip_writew(uint16_t val, chipaddr addr);
@ -360,6 +353,18 @@ void fallback_chip_writen(uint8_t *buf, chipaddr addr, size_t len);
uint16_t fallback_chip_readw(const chipaddr addr); uint16_t fallback_chip_readw(const chipaddr addr);
uint32_t fallback_chip_readl(const chipaddr addr); uint32_t fallback_chip_readl(const chipaddr addr);
void fallback_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); void fallback_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);
struct par_programmer {
void (*chip_writeb) (uint8_t val, chipaddr addr);
void (*chip_writew) (uint16_t val, chipaddr addr);
void (*chip_writel) (uint32_t val, chipaddr addr);
void (*chip_writen) (uint8_t *buf, chipaddr addr, size_t len);
uint8_t (*chip_readb) (const chipaddr addr);
uint16_t (*chip_readw) (const chipaddr addr);
uint32_t (*chip_readl) (const chipaddr addr);
void (*chip_readn) (uint8_t *buf, const chipaddr addr, size_t len);
};
extern const struct par_programmer *par_programmer;
void register_par_programmer(const struct par_programmer *pgm, const enum chipbustype buses);
/* dummyflasher.c */ /* dummyflasher.c */
#if CONFIG_DUMMY == 1 #if CONFIG_DUMMY == 1
@ -634,10 +639,6 @@ void serprog_chip_writeb(uint8_t val, chipaddr addr);
uint8_t serprog_chip_readb(const chipaddr addr); uint8_t serprog_chip_readb(const chipaddr addr);
void serprog_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); void serprog_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);
void serprog_delay(int usecs); void serprog_delay(int usecs);
int serprog_spi_send_command(unsigned int writecnt, unsigned int readcnt,
const unsigned char *writearr,
unsigned char *readarr);
int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);
#endif #endif
/* serial.c */ /* serial.c */

14
satamv.c
View File

@ -41,6 +41,17 @@ const struct pcidev_status satas_mv[] = {
#define PCI_BAR2_CONTROL 0x00c08 #define PCI_BAR2_CONTROL 0x00c08
#define GPIO_PORT_CONTROL 0x104f0 #define GPIO_PORT_CONTROL 0x104f0
static const struct par_programmer par_programmer_satamv = {
.chip_readb = satamv_chip_readb,
.chip_readw = fallback_chip_readw,
.chip_readl = fallback_chip_readl,
.chip_readn = fallback_chip_readn,
.chip_writeb = satamv_chip_writeb,
.chip_writew = fallback_chip_writew,
.chip_writel = fallback_chip_writel,
.chip_writen = fallback_chip_writen,
};
static int satamv_shutdown(void *data) static int satamv_shutdown(void *data)
{ {
physunmap(mv_bar, 0x20000); physunmap(mv_bar, 0x20000);
@ -137,11 +148,10 @@ int satamv_init(void)
mv_iobar = tmp & 0xffff; mv_iobar = tmp & 0xffff;
msg_pspew("Activating I/O BAR at 0x%04x\n", mv_iobar); msg_pspew("Activating I/O BAR at 0x%04x\n", mv_iobar);
buses_supported = BUS_PARALLEL;
/* 512 kByte with two 8-bit latches, and /* 512 kByte with two 8-bit latches, and
* 4 MByte with additional 3-bit latch. */ * 4 MByte with additional 3-bit latch. */
max_rom_decode.parallel = 4 * 1024 * 1024; max_rom_decode.parallel = 4 * 1024 * 1024;
register_par_programmer(&par_programmer_satamv, BUS_PARALLEL);
return 0; return 0;

16
satasii.c
View File

@ -42,6 +42,17 @@ const struct pcidev_status satas_sii[] = {
{}, {},
}; };
static const struct par_programmer par_programmer_satasii = {
.chip_readb = satasii_chip_readb,
.chip_readw = fallback_chip_readw,
.chip_readl = fallback_chip_readl,
.chip_readn = fallback_chip_readn,
.chip_writeb = satasii_chip_writeb,
.chip_writew = fallback_chip_writew,
.chip_writel = fallback_chip_writel,
.chip_writen = fallback_chip_writen,
};
static int satasii_shutdown(void *data) static int satasii_shutdown(void *data)
{ {
physunmap(sii_bar, SATASII_MEMMAP_SIZE); physunmap(sii_bar, SATASII_MEMMAP_SIZE);
@ -76,10 +87,11 @@ int satasii_init(void)
if ((id != 0x0680) && (!(pci_mmio_readl(sii_bar) & (1 << 26)))) if ((id != 0x0680) && (!(pci_mmio_readl(sii_bar) & (1 << 26))))
msg_pinfo("Warning: Flash seems unconnected.\n"); msg_pinfo("Warning: Flash seems unconnected.\n");
buses_supported = BUS_PARALLEL;
if (register_shutdown(satasii_shutdown, NULL)) if (register_shutdown(satasii_shutdown, NULL))
return 1; return 1;
register_par_programmer(&par_programmer_satasii, BUS_PARALLEL);
return 0; return 0;
} }

66
serprog.c
View File

@ -299,6 +299,11 @@ static int sp_stream_buffer_op(uint8_t cmd, uint32_t parmlen, uint8_t * parms)
return 0; return 0;
} }
static int serprog_spi_send_command(unsigned int writecnt, unsigned int readcnt,
const unsigned char *writearr,
unsigned char *readarr);
static int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start,
int len);
static struct spi_programmer spi_programmer_serprog = { static struct spi_programmer spi_programmer_serprog = {
.type = SPI_CONTROLLER_SERPROG, .type = SPI_CONTROLLER_SERPROG,
.max_data_read = MAX_DATA_READ_UNLIMITED, .max_data_read = MAX_DATA_READ_UNLIMITED,
@ -309,6 +314,19 @@ static struct spi_programmer spi_programmer_serprog = {
.write_256 = default_spi_write_256, .write_256 = default_spi_write_256,
}; };
static const struct par_programmer par_programmer_serprog = {
.chip_readb = serprog_chip_readb,
.chip_readw = fallback_chip_readw,
.chip_readl = fallback_chip_readl,
.chip_readn = serprog_chip_readn,
.chip_writeb = serprog_chip_writeb,
.chip_writew = fallback_chip_writew,
.chip_writel = fallback_chip_writel,
.chip_writen = fallback_chip_writen,
};
static enum chipbustype serprog_buses_supported = BUS_NONE;
int serprog_init(void) int serprog_init(void)
{ {
uint16_t iface; uint16_t iface;
@ -400,41 +418,45 @@ int serprog_init(void)
if (sp_docommand(S_CMD_Q_IFACE, 0, NULL, 2, &iface)) { if (sp_docommand(S_CMD_Q_IFACE, 0, NULL, 2, &iface)) {
msg_perr("Error: NAK to query interface version\n"); msg_perr("Error: NAK to query interface version\n");
exit(1); return 1;
} }
if (iface != 1) { if (iface != 1) {
msg_perr("Error: Unknown interface version: %d\n", iface); msg_perr("Error: Unknown interface version: %d\n", iface);
exit(1); return 1;
} }
msg_pdbg(MSGHEADER "Interface version ok.\n"); msg_pdbg(MSGHEADER "Interface version ok.\n");
if (sp_docommand(S_CMD_Q_CMDMAP, 0, NULL, 32, sp_cmdmap)) { if (sp_docommand(S_CMD_Q_CMDMAP, 0, NULL, 32, sp_cmdmap)) {
msg_perr("Error: query command map not supported\n"); msg_perr("Error: query command map not supported\n");
exit(1); return 1;
} }
sp_check_avail_automatic = 1; sp_check_avail_automatic = 1;
/* FIXME: This assumes that serprog device bustypes are always
* identical with flashrom bustype enums and that they all fit
* in a single byte.
*/
if (sp_docommand(S_CMD_Q_BUSTYPE, 0, NULL, 1, &c)) { if (sp_docommand(S_CMD_Q_BUSTYPE, 0, NULL, 1, &c)) {
msg_perr("Warning: NAK to query supported buses\n"); msg_perr("Warning: NAK to query supported buses\n");
c = BUS_NONSPI; /* A reasonable default for now. */ c = BUS_NONSPI; /* A reasonable default for now. */
} }
buses_supported = c; serprog_buses_supported = c;
msg_pdbg(MSGHEADER "Bus support: parallel=%s, LPC=%s, FWH=%s, SPI=%s\n", msg_pdbg(MSGHEADER "Bus support: parallel=%s, LPC=%s, FWH=%s, SPI=%s\n",
(c & BUS_PARALLEL) ? "on" : "off", (c & BUS_PARALLEL) ? "on" : "off",
(c & BUS_LPC) ? "on" : "off", (c & BUS_LPC) ? "on" : "off",
(c & BUS_FWH) ? "on" : "off", (c & BUS_FWH) ? "on" : "off",
(c & BUS_SPI) ? "on" : "off"); (c & BUS_SPI) ? "on" : "off");
/* Check for the minimum operational set of commands. */ /* Check for the minimum operational set of commands. */
if (buses_supported & BUS_SPI) { if (serprog_buses_supported & BUS_SPI) {
uint8_t bt = BUS_SPI; uint8_t bt = BUS_SPI;
if (sp_check_commandavail(S_CMD_O_SPIOP) == 0) { if (sp_check_commandavail(S_CMD_O_SPIOP) == 0) {
msg_perr("Error: SPI operation not supported while the " msg_perr("Error: SPI operation not supported while the "
"bustype is SPI\n"); "bustype is SPI\n");
exit(1); return 1;
} }
/* Success of any of these commands is optional. We don't need /* Success of any of these commands is optional. We don't need
the programmer to tell us its limits, but if it doesn't, we the programmer to tell us its limits, but if it doesn't, we
@ -461,40 +483,39 @@ int serprog_init(void)
spi_programmer_serprog.max_data_read = v; spi_programmer_serprog.max_data_read = v;
msg_pdbg(MSGHEADER "Maximum read-n length is %d\n", v); msg_pdbg(MSGHEADER "Maximum read-n length is %d\n", v);
} }
bt = buses_supported; bt = serprog_buses_supported;
sp_docommand(S_CMD_S_BUSTYPE, 1, &bt, 0, NULL); sp_docommand(S_CMD_S_BUSTYPE, 1, &bt, 0, NULL);
register_spi_programmer(&spi_programmer_serprog);
} }
if (buses_supported & BUS_NONSPI) { if (serprog_buses_supported & BUS_NONSPI) {
if (sp_check_commandavail(S_CMD_O_INIT) == 0) { if (sp_check_commandavail(S_CMD_O_INIT) == 0) {
msg_perr("Error: Initialize operation buffer " msg_perr("Error: Initialize operation buffer "
"not supported\n"); "not supported\n");
exit(1); return 1;
} }
if (sp_check_commandavail(S_CMD_O_DELAY) == 0) { if (sp_check_commandavail(S_CMD_O_DELAY) == 0) {
msg_perr("Error: Write to opbuf: " msg_perr("Error: Write to opbuf: "
"delay not supported\n"); "delay not supported\n");
exit(1); return 1;
} }
/* S_CMD_O_EXEC availability checked later. */ /* S_CMD_O_EXEC availability checked later. */
if (sp_check_commandavail(S_CMD_R_BYTE) == 0) { if (sp_check_commandavail(S_CMD_R_BYTE) == 0) {
msg_perr("Error: Single byte read not supported\n"); msg_perr("Error: Single byte read not supported\n");
exit(1); return 1;
} }
/* This could be translated to single byte reads (if missing), /* This could be translated to single byte reads (if missing),
* but now we don't support that. */ * but now we don't support that. */
if (sp_check_commandavail(S_CMD_R_NBYTES) == 0) { if (sp_check_commandavail(S_CMD_R_NBYTES) == 0) {
msg_perr("Error: Read n bytes not supported\n"); msg_perr("Error: Read n bytes not supported\n");
exit(1); return 1;
} }
if (sp_check_commandavail(S_CMD_O_WRITEB) == 0) { if (sp_check_commandavail(S_CMD_O_WRITEB) == 0) {
msg_perr("Error: Write to opbuf: " msg_perr("Error: Write to opbuf: "
"write byte not supported\n"); "write byte not supported\n");
exit(1); return 1;
} }
if (sp_docommand(S_CMD_Q_WRNMAXLEN, 0, NULL, 3, rbuf)) { if (sp_docommand(S_CMD_Q_WRNMAXLEN, 0, NULL, 3, rbuf)) {
@ -513,7 +534,7 @@ int serprog_init(void)
if (!sp_write_n_buf) { if (!sp_write_n_buf) {
msg_perr("Error: cannot allocate memory for " msg_perr("Error: cannot allocate memory for "
"Write-n buffer\n"); "Write-n buffer\n");
exit(1); return 1;
} }
sp_write_n_bytes = 0; sp_write_n_bytes = 0;
} }
@ -551,12 +572,12 @@ int serprog_init(void)
if (sp_check_commandavail(S_CMD_O_EXEC) == 0) { if (sp_check_commandavail(S_CMD_O_EXEC) == 0) {
msg_perr("Error: Execute operation buffer not " msg_perr("Error: Execute operation buffer not "
"supported\n"); "supported\n");
exit(1); return 1;
} }
if (sp_docommand(S_CMD_O_INIT, 0, NULL, 0, NULL)) { if (sp_docommand(S_CMD_O_INIT, 0, NULL, 0, NULL)) {
msg_perr("Error: NAK to initialize operation buffer\n"); msg_perr("Error: NAK to initialize operation buffer\n");
exit(1); return 1;
} }
if (sp_docommand(S_CMD_Q_OPBUF, 0, NULL, 2, if (sp_docommand(S_CMD_Q_OPBUF, 0, NULL, 2,
@ -572,6 +593,11 @@ int serprog_init(void)
sp_streamed_transmit_ops = 0; sp_streamed_transmit_ops = 0;
sp_streamed_transmit_bytes = 0; sp_streamed_transmit_bytes = 0;
sp_opbuf_usage = 0; sp_opbuf_usage = 0;
if (serprog_buses_supported & BUS_SPI)
register_spi_programmer(&spi_programmer_serprog);
if (serprog_buses_supported & BUS_NONSPI)
register_par_programmer(&par_programmer_serprog,
serprog_buses_supported & BUS_NONSPI);
return 0; return 0;
} }
@ -766,7 +792,7 @@ void serprog_delay(int usecs)
sp_prev_was_write = 0; sp_prev_was_write = 0;
} }
int serprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, static int serprog_spi_send_command(unsigned int writecnt, unsigned int readcnt,
const unsigned char *writearr, const unsigned char *writearr,
unsigned char *readarr) unsigned char *readarr)
{ {
@ -796,7 +822,7 @@ int serprog_spi_send_command(unsigned int writecnt, unsigned int readcnt,
* the advantage that it is much faster for most chips, but breaks those with * the advantage that it is much faster for most chips, but breaks those with
* non-contiguous address space (like AT45DB161D). When spi_read_chunked is * non-contiguous address space (like AT45DB161D). When spi_read_chunked is
* fixed this method can be removed. */ * fixed this method can be removed. */
int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) static int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len)
{ {
int i; int i;
int cur_len; int cur_len;

2
wbsio_spi.c
View File

@ -82,10 +82,10 @@ int wbsio_check_for_spi(void)
msg_pspew("\nwbsio_spibase = 0x%x\n", wbsio_spibase); msg_pspew("\nwbsio_spibase = 0x%x\n", wbsio_spibase);
register_spi_programmer(&spi_programmer_wbsio);
msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is " msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is "
"1024 kB!\n", __func__); "1024 kB!\n", __func__);
max_rom_decode.spi = 1024 * 1024; max_rom_decode.spi = 1024 * 1024;
register_spi_programmer(&spi_programmer_wbsio);
return 0; return 0;
} }