openwrt/flashrom
1
0
Fork 0
mirror of https://review.coreboot.org/flashrom.git synced 2025-10-31 05:10:41 +01:00
Code Issues Releases Wiki Activity

Various smaller flashrom improvements

Browse Source 
- Document new 'satasii' programmer in -L output and manpage.

 - Drop PCI_IO_BASE_ADDRESS, pci.h has such #defines already.

 - Beautify flashrom output and make it more consistent.
 
 - Same for the 'make' output (reordered some $CC parameters).
   Build-tested on i386, shouldn't break any builds, I think.

 - Some variable renaming and other cosmetic fixes.

Corresponding to flashrom svn r529.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
This commit is contained in:
Uwe Hermann
2009-05-17 22:57:34 +00:00
parent 525339c32b
commit eaefb48ee5
7 changed files with 27 additions and 33 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
Makefile
View File

@@ -46,7 +46,7 @@ $(PROGRAM): $(OBJS)
$(CC) $(LDFLAGS) -o $(PROGRAM) $(OBJS) $(LIBS) $(CC) $(LDFLAGS) -o $(PROGRAM) $(OBJS) $(LIBS)
flashrom.o: flashrom.c flashrom.o: flashrom.c
$(CC) -c $(CFLAGS) $(SVNDEF) $(CPPFLAGS) $< -o $@ $(CC) $(CFLAGS) $(CPPFLAGS) -c -o $@ $< $(SVNDEF)
clean: clean:
rm -f $(PROGRAM) *.o rm -f $(PROGRAM) *.o

2
flash.h
View File

@@ -560,7 +560,6 @@ void myusec_calibrate_delay(void);
/* pcidev.c */ /* pcidev.c */
#define PCI_OK 0 #define PCI_OK 0
#define PCI_NT 1 /* Not tested */ #define PCI_NT 1 /* Not tested */
#define PCI_IO_BASE_ADDRESS 0x10
extern uint32_t io_base_addr; extern uint32_t io_base_addr;
extern struct pci_access *pacc; extern struct pci_access *pacc;
@@ -670,7 +669,6 @@ void satasii_chip_writeb(uint8_t val, chipaddr addr);
uint8_t satasii_chip_readb(const chipaddr addr); uint8_t satasii_chip_readb(const chipaddr addr);
extern struct pcidev_status satas_sii[]; extern struct pcidev_status satas_sii[];
/* flashrom.c */ /* flashrom.c */
extern int verbose; extern int verbose;
#define printf_debug(x...) { if (verbose) printf(x); } #define printf_debug(x...) { if (verbose) printf(x); }

2
flashrom.8
View File

@@ -147,6 +147,8 @@ is the PCI function number of the desired NIC.
Example: Example:
.B "flashrom -p nic3com=05:04.0" .B "flashrom -p nic3com=05:04.0"
.sp .sp
.BR "* satasii" " (for flash ROMs on Silicon Image SATA/IDE controller cards)"
.sp
.BR "* dummy" " (just prints all operations and accesses)" .BR "* dummy" " (just prints all operations and accesses)"
.TP .TP
.B "\-h, \-\-help" .B "\-h, \-\-help"

1
flashrom.c
View File

@@ -543,6 +543,7 @@ int main(int argc, char *argv[])
printf("\nSupported PCI devices flashrom can use " printf("\nSupported PCI devices flashrom can use "
"as programmer:\n\n"); "as programmer:\n\n");
print_supported_pcidevs(nics_3com); print_supported_pcidevs(nics_3com);
print_supported_pcidevs(satas_sii);
exit(0); exit(0);
} }

12
pcidev.c
View File

@@ -42,16 +42,16 @@ uint32_t pcidev_validate(struct pci_dev *dev, struct pcidev_status *devs)
continue; continue;
/* Don't use dev->base_addr[0], won't work on older libpci. */ /* Don't use dev->base_addr[0], won't work on older libpci. */
addr = pci_read_long(dev, PCI_IO_BASE_ADDRESS) & ~0x03; addr = pci_read_long(dev, PCI_BASE_ADDRESS_0) & ~0x03;
printf("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x)\n", printf("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x).\n",
devs[i].vendor_name, devs[i].device_name, dev->vendor_id, devs[i].vendor_name, devs[i].device_name, dev->vendor_id,
dev->device_id, dev->bus, dev->dev, dev->func); dev->device_id, dev->bus, dev->dev, dev->func);
if (devs[i].status == PCI_NT) { if (devs[i].status == PCI_NT) {
printf("===\nThis PCI device is UNTESTED. Please email " printf("===\nThis PCI device is UNTESTED. Please "
"a report including the 'flashrom -p xxxxxx'\n" "report the 'flashrom -p xxxx' output \n"
"output to flashrom@coreboot.org if it works " "to flashrom@coreboot.org if it works "
"for you. Thank you for your help!\n===\n"); "for you. Thank you for your help!\n===\n");
} }
@@ -98,7 +98,7 @@ uint32_t pcidev_init(uint16_t vendor_id, struct pcidev_status *devs)
exit(1); exit(1);
} else if (found > 1) { } else if (found > 1) {
fprintf(stderr, "Error: Multiple supported PCI devices found. " fprintf(stderr, "Error: Multiple supported PCI devices found. "
"Please use 'flashrom -p xxxxxx=bb:dd.f' \n" "Use 'flashrom -p xxxx=bb:dd.f' \n"
"to explicitly select the card with the given BDF " "to explicitly select the card with the given BDF "
"(PCI bus, device, function).\n"); "(PCI bus, device, function).\n");
exit(1); exit(1);

8
physmap.c
View File

@@ -81,18 +81,18 @@ void physunmap(void *virt_addr, size_t len)
void *physmap(const char *descr, unsigned long phys_addr, size_t len) void *physmap(const char *descr, unsigned long phys_addr, size_t len)
{ {
if (len == 0) { if (len == 0) {
printf_debug("Not mapping %s, zero size at 0x%08lx\n", printf_debug("Not mapping %s, zero size at 0x%08lx.\n",
descr, phys_addr); descr, phys_addr);
return NULL; return NULL;
} }
if ((getpagesize() - 1) & len) { if ((getpagesize() - 1) & len) {
fprintf(stderr, "Mapping %s at 0x%08lx, unaligned size 0x%lx\n", fprintf(stderr, "Mapping %s at 0x%08lx, unaligned size 0x%lx.\n",
descr, phys_addr, (unsigned long)len); descr, phys_addr, (unsigned long)len);
} }
if ((getpagesize() - 1) & phys_addr) { if ((getpagesize() - 1) & phys_addr) {
fprintf(stderr, "Mapping %s, 0x%lx bytes at unaligned 0x%08lx\n", fprintf(stderr, "Mapping %s, 0x%lx bytes at unaligned 0x%08lx.\n",
descr, (unsigned long)len, phys_addr); descr, (unsigned long)len, phys_addr);
} }

33
sata_sii.c
View File

@@ -15,7 +15,7 @@
* *
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, , 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
/* Datasheets can be found on http://www.siliconimage.com. Great thanks! */ /* Datasheets can be found on http://www.siliconimage.com. Great thanks! */
@@ -39,6 +39,7 @@ struct pcidev_status satas_sii[] = {
{0x1095, 0x3124, PCI_NT, "Silicon Image", "SiI 3124 PCI-X Serial ATA Controller"}, {0x1095, 0x3124, PCI_NT, "Silicon Image", "SiI 3124 PCI-X Serial ATA Controller"},
{0x1095, 0x3132, PCI_OK, "Silicon Image", "SiI 3132 Serial ATA Raid II Controller"}, {0x1095, 0x3132, PCI_OK, "Silicon Image", "SiI 3132 Serial ATA Raid II Controller"},
{0x1095, 0x3512, PCI_NT, "Silicon Image", "SiI 3512 [SATALink/SATARaid] Serial ATA Controller"}, {0x1095, 0x3512, PCI_NT, "Silicon Image", "SiI 3512 [SATALink/SATARaid] Serial ATA Controller"},
{}, {},
}; };
@@ -50,33 +51,27 @@ int satasii_init(void)
get_io_perms(); get_io_perms();
pcidev_init(PCI_VENDOR_ID_SII, satas_sii); pcidev_init(PCI_VENDOR_ID_SII, satas_sii);
id = pcidev_dev->device_id; id = pcidev_dev->device_id;
if ((id == 0x3132) || (id == 0x3124)) { if ((id == 0x3132) || (id == 0x3124)) {
/* BAR 0, offset 0x70 */ addr = pci_read_long(pcidev_dev, PCI_BASE_ADDRESS_0) & ~0x07;
addr = pci_read_long(pcidev_dev, PCI_IO_BASE_ADDRESS) & ~0x07;
reg_offset = 0x70; reg_offset = 0x70;
} else { } else {
/* BAR 5, offset 0x50 */ addr = pci_read_long(pcidev_dev, PCI_BASE_ADDRESS_5) & ~0x07;
addr = pci_read_long(pcidev_dev, PCI_IO_BASE_ADDRESS + (5 * 4)) & ~0x07;
reg_offset = 0x50; reg_offset = 0x50;
} }
sii_bar = physmap("SATA SIL registers", addr, 0x100); sii_bar = physmap("SATA SIL registers", addr, 0x100) + reg_offset;
sii_bar += reg_offset;
/* check if rom cycle are OK */ /* Check if ROM cycle are OK. */
if (!(mmio_readl(sii_bar)) & (1 << 26)) { if (!(mmio_readl(sii_bar)) & (1 << 26))
printf("Warning: Flash seems unconnected\n"); printf("Warning: Flash seems unconnected\n");
}
return 0; return 0;
} }
int satasii_shutdown(void) int satasii_shutdown(void)
{ {
free(pcidev_bdf); free(pcidev_bdf);
pci_cleanup(pacc); pci_cleanup(pacc);
#if defined(__FreeBSD__) || defined(__DragonFly__) #if defined(__FreeBSD__) || defined(__DragonFly__)
@@ -96,21 +91,19 @@ void satasii_unmap(void *virt_addr, size_t len)
void satasii_chip_writeb(uint8_t val, chipaddr addr) void satasii_chip_writeb(uint8_t val, chipaddr addr)
{ {
uint32_t ctrl_reg, data_reg;
uint32_t ctrl_reg, addr_reg;
while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ;
/* Mask out unused/reserved bits, set writes and start transaction */ /* Mask out unused/reserved bits, set writes and start transaction. */
ctrl_reg &= 0xfcf80000; ctrl_reg &= 0xfcf80000;
ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff); ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff);
addr_reg = (mmio_readl((sii_bar + 4)) & ~0xff) | val; data_reg = (mmio_readl((sii_bar + 4)) & ~0xff) | val;
mmio_writel(addr_reg, (sii_bar + 4)); mmio_writel(data_reg, (sii_bar + 4));
mmio_writel(ctrl_reg, sii_bar); mmio_writel(ctrl_reg, sii_bar);
while (mmio_readl(sii_bar) & (1 << 25)) ; while (mmio_readl(sii_bar) & (1 << 25)) ;
} }
uint8_t satasii_chip_readb(const chipaddr addr) uint8_t satasii_chip_readb(const chipaddr addr)
@@ -119,13 +112,13 @@ uint8_t satasii_chip_readb(const chipaddr addr)
while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ;
/* Mask out unused/reserved bits, set reads and start transaction */ /* Mask out unused/reserved bits, set reads and start transaction. */
ctrl_reg &= 0xfcf80000; ctrl_reg &= 0xfcf80000;
ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff); ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff);
mmio_writel(ctrl_reg, sii_bar); mmio_writel(ctrl_reg, sii_bar);
while ((mmio_readl(sii_bar)) & (1 << 25)) ; while (mmio_readl(sii_bar) & (1 << 25)) ;
return (mmio_readl(sii_bar + 4)) & 0xff; return (mmio_readl(sii_bar + 4)) & 0xff;
} }